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author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2019-10-17 12:40:39 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-18 12:51:13 +0200 |
commit | 1cf24373c00b05cf1a1e08ba37522c0593e57106 (patch) | |
tree | 00a4c168b67445f7601269ee3d1cd276cd9ad659 /arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h | |
parent | e096d05356e8f7af0196e00d9747469e9ea61ba8 (diff) | |
download | barebox-1cf24373c00b05cf1a1e08ba37522c0593e57106.tar.gz barebox-1cf24373c00b05cf1a1e08ba37522c0593e57106.tar.xz |
net: designware: socfpga: fix phy setup for Arria10
Barebox-version of the Linux v5.2 patch:
40ae25505fe834648ce4aa70b073ee934942bfdb
net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
the Cyclone5 and Arria5:
- The emac PHY setup bits are in separate registers.
- The PTP reference clock select mask is different.
- The register to enable the emac signal from FPGA is different.
Thus, this patch creates a separate function for setting the phy modes on
Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
"altr,socfpga-stmmac-a10-s10".
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
The new DTS binding is already part of v2019.10.0 and the driver doesn't
probe on Arria10 without the new binding introduced in this patch.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h')
0 files changed, 0 insertions, 0 deletions