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author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2018-07-31 12:44:39 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-08-08 09:22:48 +0200 |
commit | 8a680e3c9b5dd8470b7437654877d5439e9a6407 (patch) | |
tree | d2ca86ad8029b3b70c5754cbdc43618740b5f5d9 /arch/arm/mach-socfpga/include/mach/generic.h | |
parent | 1466d7d0e485fe43258aea423d2e4deba7d83c1e (diff) | |
download | barebox-8a680e3c9b5dd8470b7437654877d5439e9a6407.tar.gz barebox-8a680e3c9b5dd8470b7437654877d5439e9a6407.tar.xz |
ARM: socfpga: Arria10: support programming FPGA in PBL
Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.
It works like this:
1. boot ROM fetches the PBL from MMC
2. read the MBR from MMC (this depends on the setup done by the boot ROM)
3. read the Bitstream from the MMC and program the FPGA
4. re-read the barebox image from MMC, this time with the full barebox
that is appended to the PBL
5. jump into the full barebox
Only supported boot device is eMMC.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/generic.h')
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/generic.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h index 5fcbc9ecf5..72391f3552 100644 --- a/arch/arm/mach-socfpga/include/mach/generic.h +++ b/arch/arm/mach-socfpga/include/mach/generic.h @@ -46,7 +46,43 @@ static inline void socfpga_cyclone5_qspi_init(void) } #endif #if defined(CONFIG_ARCH_SOCFPGA_ARRIA10) +void socfpga_arria10_mmc_init(void); +void socfpga_arria10_timer_init(void); +int arria10_prepare_mmc(int barebox, int bitstream); +void arria10_start_image(int offset); +int arria10_load_fpga(int offset, int size); +int arria10_device_init(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll, + uint32_t *pinmux); enum bootsource arria10_get_bootsource(void); +#else +static inline void socfpga_arria10_mmc_init(void) +{ + return; +} + +static inline void socfpga_arria10_timer_init(void) +{ + return; +} +static void arria10_prepare_mmc(int barebox, int bitstream) +{ + return; +} +static void arria10_start_image(int offset) +{ + return; +} +static int arria10_load_fpga(int offset, int size) +{ + return; +} +static int arria10_device_init(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll, + uint32_t *pinmux) +{ + return 0; +} #endif static inline void __udelay(unsigned us) |