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| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2018-06-29 13:55:01 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-07-02 06:04:19 +0200 |
| commit | 26cab6f406b1f5d9049870a35bc119b126378e96 (patch) | |
| tree | 4a56d0f8ab3dbfd5348290290192c18133735cc2 /arch/arm/mach-socfpga | |
| parent | 9fe4ab90d0c8aab15fee9de78a804dd2d564f180 (diff) | |
| download | barebox-26cab6f406b1f5d9049870a35bc119b126378e96.tar.gz barebox-26cab6f406b1f5d9049870a35bc119b126378e96.tar.xz | |
arm: arria10: enable errata 794072 and 845369
Enable workarounds for two of the errata the CPU is affected
with.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/arria10-init.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c index 07256da1db..f016b84bb7 100644 --- a/arch/arm/mach-socfpga/arria10-init.c +++ b/arch/arm/mach-socfpga/arria10-init.c @@ -14,6 +14,7 @@ #include <mach/generic.h> #include <asm/io.h> #include <asm/cache-l2x0.h> +#include <asm/errata.h> #include <asm/system.h> #define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ @@ -70,6 +71,9 @@ static void arria10_initialize_security_policies(void) /* BootROM leaves the L2X0 in a weird state. Always disable L2X0 for now. */ l2c310_disable(l2x0_base); + enable_arm_errata_794072_war(); + enable_arm_errata_845369_war(); + /* Put OCRAM in non-secure */ writel(0x003f0000, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0); writel(0x1, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN); |