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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-26 14:54:51 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-11-02 08:49:01 +0100 |
| commit | b295e00bfab3ee1e2d157aea932803ad598ee878 (patch) | |
| tree | 49db2a929d132e175d01bff2cc2076379898e2c6 /arch/arm/mach-socfpga | |
| parent | 934ff9eccb0f64261f6711b8a14764727b550564 (diff) | |
| download | barebox-b295e00bfab3ee1e2d157aea932803ad598ee878.tar.gz barebox-b295e00bfab3ee1e2d157aea932803ad598ee878.tar.xz | |
ARM: SoCFPGA: arria10: Fix DMA accesses at addresses < 256KiB
Setting BIT(1) in the ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE results in
mapping the OCRAM to 0x0, at least for the CPU. Peripherals doing
DMA like the SDMMC controller see the SDRAM instead. Linux happens
to use this low memory for DMA sometimes and things explode nicely
at that point.
Clear the OCRAM mapping so that both the CPU and DMA controllers access
SDRAM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20221026125451.3357318-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/arria10-init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c index 2fa44c21c5..93bc3368d3 100644 --- a/arch/arm/mach-socfpga/arria10-init.c +++ b/arch/arm/mach-socfpga/arria10-init.c @@ -174,7 +174,7 @@ void arria10_init(struct arria10_mainpll_cfg *mainpll, * Enable address filtering (Bit[0]) */ writel(0x00000001, ARRIA10_MPUL2_ADRFLTR_START); - writel(0x00000002, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE); + writel(0x00000000, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE); arria10_reset_peripherals(); |