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| author | Stefan Kerkmann <s.kerkmann@pengutronix.de> | 2023-12-14 17:10:31 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-12-15 12:07:31 +0100 |
| commit | db5fb2d3e3c20086a066a9c840a62fcabaf53776 (patch) | |
| tree | 1037c08fa69392856f7848176fefe959c459dec8 /arch/arm/mach-socfpga | |
| parent | 5fc4ec28e6d8b375883e5c9d486a9e7dcef5bf08 (diff) | |
| download | barebox-db5fb2d3e3c20086a066a9c840a62fcabaf53776.tar.gz barebox-db5fb2d3e3c20086a066a9c840a62fcabaf53776.tar.xz | |
arm: mach-socfpga: detect workaround for dram controller erratum
To work around an erratum, the previous booting stage may have increased the
amount of rows to fake having 4G of RAM. In that case, we assume the previous
booting stage will have fixed up a proper memory size into the device tree and
don't use the calculated dram size. The erratum itself appears to be
undocumented by Altera/Intel and the workaround was introduced in the Alteras
fork of U-Boot back in 2014 and ported to mainline later, the linked FogBugz
issue is unfortunately not accessible.
[1] github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Link: https://lore.barebox.org/20231214-fix-socfpga-dram-errata-workaround-v1-1-abfab95e7f69@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/cyclone5-generic.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c index ae8142b31c..0cb46b51e9 100644 --- a/arch/arm/mach-socfpga/cyclone5-generic.c +++ b/arch/arm/mach-socfpga/cyclone5-generic.c @@ -128,7 +128,8 @@ void socfpga_cyclone5_timer_init(void) static int socfpga_detect_sdram(void) { void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS; - uint32_t dramaddrw, ctrlwidth, memsize; + uint32_t dramaddrw, ctrlwidth; + uint64_t memsize; int colbits, rowbits, bankbits; int width_bytes; @@ -153,12 +154,20 @@ static int socfpga_detect_sdram(void) break; } - memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes; + memsize = (1ULL << colbits) * (1ULL << rowbits) * (1ULL << bankbits) * + width_bytes; - pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n", + pr_debug( + "%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08llx\n", __func__, colbits, rowbits, bankbits, width_bytes, memsize); - arm_add_mem_device("ram0", 0x0, memsize); + /* To work around an erratum in the dram controller, the previous booting + * stage may have increased the amount of rows to fake having 4G of RAM. In + * that case, we assume the previous booting stage will have fixed up a + * proper memory size into the device tree and don't add a bank here */ + if (memsize < SZ_4G) { + arm_add_mem_device("ram0", 0x0, memsize); + } return 0; } |