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| author | Ahmad Fatoum <ahmad@a3f.at> | 2020-03-30 16:39:09 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-05-08 14:52:41 +0200 |
| commit | 2e45f03730101082633bd50d3d14ac0eac776de8 (patch) | |
| tree | f9d53f5983e3e3c1efcd31db455ff2f77eeb9d14 /arch/arm/mach-stm32mp/include | |
| parent | 8974b63acff909ca10c0a21d3e3dbe463cbfb191 (diff) | |
| download | barebox-2e45f03730101082633bd50d3d14ac0eac776de8.tar.gz barebox-2e45f03730101082633bd50d3d14ac0eac776de8.tar.xz | |
ARM: stm32mp: init: detect Revision Z and 800 MHz profiles
Revision A was 0x1000 and B was 0x2000, so I assumed the next would
be revision C valued 0x3000. Alas, it's revision Z with 0x2001...
Change the code accordingly and add detection for the new 800Mhz
profiles.
Code taken from U-Boot commit
cf0818b477 ("stm32mp1: support of STM32MP15x Rev.Z") and
Patch[1] "stm32mp1: add 800 MHz profile support".
[1]: https://st-md-mailman.stormreply.com/pipermail/uboot-stm32/2020-February/002170.html
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-stm32mp/include')
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/revision.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h index 387201421d..2eb4d44b33 100644 --- a/arch/arm/mach-stm32mp/include/mach/revision.h +++ b/arch/arm/mach-stm32mp/include/mach/revision.h @@ -6,17 +6,33 @@ #ifndef __MACH_CPUTYPE_H__ #define __MACH_CPUTYPE_H__ -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/ + +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) + * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI + * 153X: 2x Cortex-A7, Cortex-M4, CAN FD + * 151X: 1x Cortex-A7, Cortex-M4 + * XXXA: Cortex-A7 @ 650 MHz + * XXXC: Cortex-A7 @ 650 MHz + Secure Boot + HW Crypto + * XXXD: Cortex-A7 @ 800 MHz + * XXXF: Cortex-A7 @ 800 MHz + Secure Boot + HW Crypto + */ #define CPU_STM32MP157Cxx 0x05000000 #define CPU_STM32MP157Axx 0x05000001 #define CPU_STM32MP153Cxx 0x05000024 #define CPU_STM32MP153Axx 0x05000025 #define CPU_STM32MP151Cxx 0x0500002E #define CPU_STM32MP151Axx 0x0500002F +#define CPU_STM32MP157Fxx 0x05000080 +#define CPU_STM32MP157Dxx 0x05000081 +#define CPU_STM32MP153Fxx 0x050000A4 +#define CPU_STM32MP153Dxx 0x050000A5 +#define CPU_STM32MP151Fxx 0x050000AE +#define CPU_STM32MP151Dxx 0x050000AF /* silicon revisions */ #define CPU_REV_A 0x1000 #define CPU_REV_B 0x2000 +#define CPU_REV_Z 0x2001 int stm32mp_silicon_revision(void); int stm32mp_cputype(void); |