Merge branch 'for-next/stm32'

5 files changed, 76 insertions, 15 deletions

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index d059dbda56..bc0a48d64c 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -6,15 +6,23 @@ config ARCH_NR_GPIO
 	int
 	default 416
 
+config ARCH_STM32MP13
+	select ARM_PSCI_CLIENT
+	bool
+
 config ARCH_STM32MP157
 	select ARM_PSCI_CLIENT
 	bool
 
+config MACH_STM32MP13XX_DK
+	select ARCH_STM32MP13
+	bool "STM32MP137F DK board"
+
 config MACH_STM32MP15XX_DKX
 	select ARCH_STM32MP157
 	bool "STM32MP157 DK1 and DK2 boards"
 	help
-	  builds a single barebox-stm32mp15xx-dkx.img that can be deployed
+	  builds a single barebox-stm32mp15xx-dkx.stm32 that can be deployed
 	  as SSBL on both the stm32mp157a-dk1 and stm32mp157c-dk2
 
 config MACH_LXA_MC1
@@ -29,7 +37,7 @@ config MACH_STM32MP15X_EV1
 	select ARCH_STM32MP157
 	bool "STM32MP15X-EV1 board"
 	help
-	  builds a single barebox-stm32mp15x-ev1.img that can be deployed
+	  builds a single barebox-stm32mp15x-ev1.stm32 that can be deployed
 	  as SSBL on any STM32MP15X-EVAL platform, like the
 	  STM32MP157C-EV1
 
@@ -37,7 +45,14 @@ config MACH_PROTONIC_STM32MP1
 	select ARCH_STM32MP157
 	bool "Protonic PRTT1L family of boards"
 	help
-	  Builds all barebox-prtt1*.img that can be deployed as SSBL
+	  Builds all barebox-prtt1*.stm32 that can be deployed as SSBL
 	  on the respective PRTT1L family board
 
+config MACH_PHYTEC_PHYCORE_STM32MP1
+	select ARCH_STM32MP157
+	bool "phyCORE-STM32MP1"
+	help
+	  builds an additional barebox-phytec-phycore.stm32
+	  that can be deployed as SSBL on the phyCORE-STM32MP1
+
 endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 4163bd176b..86c13b8fca 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -2,4 +2,5 @@
 
 obj-y := init.o
 obj-pbl-y := ddrctrl.o
+pbl-y := bl33-generic.o
 obj-$(CONFIG_BOOTM) += stm32image.o
diff --git a/arch/arm/mach-stm32mp/bl33-generic.c b/arch/arm/mach-stm32mp/bl33-generic.c
new file mode 100644
index 0000000000..6f779b19cf
--- /dev/null
+++ b/arch/arm/mach-stm32mp/bl33-generic.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <mach/entry.h>
+#include <debug_ll.h>
+
+/*
+ * barebox-dt-2nd.img expects being loaded at an offset, so the
+ * stack can grow down from entry point. The STM32MP TF-A default
+ * is to not have an offset. This stm32mp specific entry points
+ * avoids this issue by setting up a 64 byte stack after end of
+ * barebox and by asking the memory controller about RAM size
+ * instead of parsing it out of the DT.
+ *
+ * When using OP-TEE, ensure CONFIG_OPTEE_SIZE is appopriately set.
+ */
+
+ENTRY_FUNCTION(start_stm32mp_bl33, r0, r1, r2)
+{
+	stm32mp_cpu_lowlevel_init();
+
+	putc_ll('>');
+
+	stm32mp1_barebox_entry((void *)r2);
+}
diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c
index 7f2013c22d..ed211cf58e 100644
--- a/arch/arm/mach-stm32mp/ddrctrl.c
+++ b/arch/arm/mach-stm32mp/ddrctrl.c
@@ -9,6 +9,7 @@
 #include <mach/ddr_regs.h>
 #include <mach/entry.h>
 #include <mach/stm32.h>
+#include <mach/revision.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
 #include <pbl.h>
@@ -24,12 +25,12 @@
 #define ADDRMAP2_COL_B5		GENMASK(27, 24)
 
 #define ADDRMAP3_COL_B6		GENMASK( 3,  0)
-#define ADDRMAP3_COL_B7		GENMASK(12,  8)
-#define ADDRMAP3_COL_B8		GENMASK(20, 16)
-#define ADDRMAP3_COL_B9		GENMASK(28, 24)
+#define ADDRMAP3_COL_B7		GENMASK(11,  8)
+#define ADDRMAP3_COL_B8		GENMASK(19, 16)
+#define ADDRMAP3_COL_B9		GENMASK(27, 24)
 
-#define ADDRMAP4_COL_B10	GENMASK( 4,  0)
-#define ADDRMAP4_COL_B11	GENMASK(12,  8)
+#define ADDRMAP4_COL_B10	GENMASK( 3,  0)
+#define ADDRMAP4_COL_B11	GENMASK(11,  8)
 
 #define ADDRMAP5_ROW_B0		GENMASK( 3,  0)
 #define ADDRMAP5_ROW_B1		GENMASK(11,  8)
@@ -62,7 +63,8 @@ enum ddrctrl_buswidth {
 };
 
 static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
-					     enum ddrctrl_buswidth buswidth)
+					     enum ddrctrl_buswidth buswidth,
+					     unsigned nb_bytes)
 {
 	unsigned banks = 3, cols = 12, rows = 16;
 	u32 reg;
@@ -99,21 +101,27 @@ static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
 	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B13)) rows--;
 	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B12)) rows--;
 
-	return memory_sdram_size(cols, rows, BIT(banks), 4 / BIT(buswidth));
+	return memory_sdram_size(cols, rows, BIT(banks),
+				 DIV_ROUND_UP(nb_bytes, BIT(buswidth)));
 }
 
-static inline unsigned ddrctrl_ramsize(void __iomem *base)
+static inline unsigned ddrctrl_ramsize(void __iomem *base, unsigned nb_bytes)
 {
 	struct stm32mp1_ddrctl __iomem *ddrctl = base;
 	unsigned buswidth = readl(&ddrctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
 	buswidth >>= DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
 
-	return ddrctrl_addrmap_ramsize(ddrctl, buswidth);
+	return ddrctrl_addrmap_ramsize(ddrctl, buswidth, nb_bytes);
 }
 
 static inline unsigned stm32mp1_ddrctrl_ramsize(void)
 {
-	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE));
+	u32 nb_bytes = 4;
+
+	if (cpu_stm32_is_stm32mp13())
+		nb_bytes /= 2;
+
+	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE), nb_bytes);
 }
 
 void __noreturn stm32mp1_barebox_entry(void *boarddata)
@@ -126,17 +134,22 @@ static int stm32mp1_ddr_probe(struct device_d *dev)
 {
 	struct resource *iores;
 	void __iomem *base;
+	unsigned long nb_bytes;
 
 	iores = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(iores))
 		return PTR_ERR(iores);
 	base = IOMEM(iores->start);
 
-	return arm_add_mem_device("ram0", STM32_DDR_BASE, ddrctrl_ramsize(base));
+	nb_bytes = (unsigned long)device_get_match_data(dev);
+
+	return arm_add_mem_device("ram0", STM32_DDR_BASE,
+				  ddrctrl_ramsize(base, nb_bytes));
 }
 
 static __maybe_unused struct of_device_id stm32mp1_ddr_dt_ids[] = {
-	{ .compatible = "st,stm32mp1-ddr" },
+	{ .compatible = "st,stm32mp1-ddr", .data = (void *)4 },
+	{ .compatible = "st,stm32mp13-ddr", .data = (void *)2 },
 	{ /* sentinel */ }
 };
 
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
index 2ef8ef30c3..c141b925a1 100644
--- a/arch/arm/mach-stm32mp/include/mach/revision.h
+++ b/arch/arm/mach-stm32mp/include/mach/revision.h
@@ -32,6 +32,14 @@
 #define CPU_STM32MP151Fxx	0x050000AE
 #define CPU_STM32MP151Dxx	0x050000AF
 
+#define cpu_stm32_is(mask, val) ({ \
+	u32 type; \
+	__stm32mp_get_cpu_type(&type) == 0 ? (type & mask) == val : 0; \
+})
+
+#define cpu_stm32_is_stm32mp15() cpu_stm32_is(0xFFFF0000, 0x05000000)
+#define cpu_stm32_is_stm32mp13() cpu_stm32_is(0xFFFF0000, 0x05010000)
+
 /* silicon revisions */
 #define CPU_REV_A	0x1000
 #define CPU_REV_B	0x2000