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| author | Lucas Stach <dev@lynxeye.de> | 2013-06-30 23:08:49 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-07-02 08:36:09 +0200 |
| commit | 3cfd3be736edf6fea41b03c00023dba88a2ff11e (patch) | |
| tree | f2682998ec00ccf9d584f9e613c3f78731bc8436 /arch/arm/mach-tegra/include/mach/tegra20-car.h | |
| parent | c16730e3c66bcab245aac993ce924caa129ca23d (diff) | |
| download | barebox-3cfd3be736edf6fea41b03c00023dba88a2ff11e.tar.gz barebox-3cfd3be736edf6fea41b03c00023dba88a2ff11e.tar.xz | |
tegra: add peripheral clocks
Only UART clocks are included for now, but the code should cover
other peripherals needs, too.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/tegra20-car.h')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/tegra20-car.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h index b770ae3f11..d4cb2387f3 100644 --- a/arch/arm/mach-tegra/include/mach/tegra20-car.h +++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h @@ -146,6 +146,55 @@ #define CRC_PLLE_BASE 0x0e8 #define CRC_PLLE_MISC 0x0ec +#define CRC_CLK_SOURCE_I2S1 0x100 +#define CRC_CLK_SOURCE_I2S2 0x104 +#define CRC_CLK_SOURCE_SPDIF_OUT 0x108 +#define CRC_CLK_SOURCE_SPDIF_IN 0x10c +#define CRC_CLK_SOURCE_PWM 0x110 +#define CRC_CLK_SOURCE_SPI 0x114 +#define CRC_CLK_SOURCE_SBC1 0x134 +#define CRC_CLK_SOURCE_SBC2 0x118 +#define CRC_CLK_SOURCE_SBC3 0x11c +#define CRC_CLK_SOURCE_SBC4 0x1b4 +#define CRC_CLK_SOURCE_XIO 0x120 +#define CRC_CLK_SOURCE_TWC 0x12c +#define CRC_CLK_SOURCE_IDE 0x144 +#define CRC_CLK_SOURCE_NDFLASH 0x160 +#define CRC_CLK_SOURCE_VFIR 0x168 +#define CRC_CLK_SOURCE_SDMMC1 0x150 +#define CRC_CLK_SOURCE_SDMMC2 0x154 +#define CRC_CLK_SOURCE_SDMMC3 0x1bc +#define CRC_CLK_SOURCE_SDMMC4 0x164 +#define CRC_CLK_SOURCE_CVE 0x140 +#define CRC_CLK_SOURCE_TVO 0x188 +#define CRC_CLK_SOURCE_TVDAC 0x194 +#define CRC_CLK_SOURCE_HDMI 0x18c +#define CRC_CLK_SOURCE_DISP1 0x138 +#define CRC_CLK_SOURCE_DISP2 0x13c +#define CRC_CLK_SOURCE_CSITE 0x1d4 +#define CRC_CLK_SOURCE_LA 0x1f8 +#define CRC_CLK_SOURCE_OWR 0x1cc +#define CRC_CLK_SOURCE_NOR 0x1d0 +#define CRC_CLK_SOURCE_MIPI 0x174 +#define CRC_CLK_SOURCE_I2C1 0x124 +#define CRC_CLK_SOURCE_I2C2 0x198 +#define CRC_CLK_SOURCE_I2C3 0x1b8 +#define CRC_CLK_SOURCE_DVC 0x128 +#define CRC_CLK_SOURCE_UARTA 0x178 +#define CRC_CLK_SOURCE_UARTB 0x17c +#define CRC_CLK_SOURCE_UARTC 0x1a0 +#define CRC_CLK_SOURCE_UARTD 0x1c0 +#define CRC_CLK_SOURCE_UARTE 0x1c4 +#define CRC_CLK_SOURCE_3D 0x158 +#define CRC_CLK_SOURCE_2D 0x15c +#define CRC_CLK_SOURCE_MPE 0x170 +#define CRC_CLK_SOURCE_EPP 0x16c +#define CRC_CLK_SOURCE_HOST1X 0x180 +#define CRC_CLK_SOURCE_VDE 0x1c8 +#define CRC_CLK_SOURCE_VI 0x148 +#define CRC_CLK_SOURCE_VI_SENSOR 0x1a8 +#define CRC_CLK_SOURCE_EMC 0x19c + #define CRC_RST_DEV_L_SET 0x300 #define CRC_RST_DEV_L_CACHE2 (1 << 31) #define CRC_RST_DEV_L_VCP (1 << 29) |