| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | tegra: set AHB clock rate early | Lucas Stach | 2014-02-27 | 1 | -0/+4 |
| * | tegra: add lowlevel DVC | Lucas Stach | 2014-02-27 | 1 | -0/+8 |
| * | tegra: switch main CPU complex to PLLX early | Lucas Stach | 2013-12-04 | 1 | -0/+32 |
| * | tegra: speed up system bus | Lucas Stach | 2013-12-04 | 1 | -0/+12 |
| * | tegra: add peripheral clocks | Lucas Stach | 2013-07-02 | 1 | -0/+49 |
| * | tegra: add new clock framework driver | Lucas Stach | 2013-07-02 | 1 | -0/+36 |
| * | tegra: deduplicate clk defines | Lucas Stach | 2013-07-02 | 1 | -60/+30 |
| * | tegra: add common lowlevel startup | Lucas Stach | 2013-04-14 | 1 | -0/+157 |
| * | tegra: add driver for the clock and reset module | Lucas Stach | 2013-04-14 | 1 | -0/+22 |
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