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| author | Lucas Stach <dev@lynxeye.de> | 2013-06-30 23:08:48 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-07-02 08:36:09 +0200 |
| commit | c16730e3c66bcab245aac993ce924caa129ca23d (patch) | |
| tree | d3be5ef31ac92482ede2db00a782781de22c7188 /arch/arm/mach-tegra/include/mach/tegra20-car.h | |
| parent | acc791fb107845f0a6e44ae2e1df392963950243 (diff) | |
| download | barebox-c16730e3c66bcab245aac993ce924caa129ca23d.tar.gz barebox-c16730e3c66bcab245aac993ce924caa129ca23d.tar.xz | |
tegra: add new clock framework driver
This removes the existing Tegra CAR driver and replaces it with code
ported from the Linux clock framework.
In the current state only the relevant PLLs are supported, but this is
no functional regression from the existing code.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/tegra20-car.h')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/tegra20-car.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h index 54c74c7717..b770ae3f11 100644 --- a/arch/arm/mach-tegra/include/mach/tegra20-car.h +++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h @@ -82,6 +82,39 @@ #define CRC_OSC_CTRL_PLL_REF_DIV_SHIFT 28 #define CRC_OSC_CTRL_PLL_REF_DIV_MASK (0x3 << CRC_OSC_CTRL_PLL_REF_DIV_SHIFT) +#define CRC_PLL_BASE_LOCK 27 +#define CRC_PLLE_MISC_LOCK 11 + +#define CRC_PLL_MISC_LOCK_ENABLE 18 +#define CRC_PLLDU_MISC_LOCK_ENABLE 22 +#define CRC_PLLE_MISC_LOCK_ENABLE 9 + +#define CRC_PLLS_BASE 0x0f0 +#define CRC_PLLS_MISC 0x0f4 + +#define CRC_PLLC_BASE 0x080 +#define CRC_PLLC_OUT 0x084 +#define CRC_PLLC_MISC 0x08c + +#define CRC_PLLM_BASE 0x090 +#define CRC_PLLM_OUT 0x094 +#define CRC_PLLM_MISC 0x09c + +#define CRC_PLLP_BASE 0x0a0 +#define CRC_PLLP_OUTA 0x0a4 +#define CRC_PLLP_OUTB 0x0a8 +#define CRC_PLLP_MISC 0x0ac + +#define CRC_PLLA_BASE 0x0b0 +#define CRC_PLLA_OUT 0x0b4 +#define CRC_PLLA_MISC 0x0bc + +#define CRC_PLLU_BASE 0x0c0 +#define CRC_PLLU_MISC 0x0cc + +#define CRC_PLLD_BASE 0x0d0 +#define CRC_PLLD_MISC 0x0dc + #define CRC_PLLX_BASE 0x0e0 #define CRC_PLLX_BASE_BYPASS (1 << 31) #define CRC_PLLX_BASE_ENABLE (1 << 30) @@ -110,6 +143,9 @@ #define CRC_PLLX_MISC_VCOCON_SHIFT 0 #define CRC_PLLX_MISC_VCOCON_MASK (0xf << CRC_PLLX_MISC_VCOCON_SHIFT) +#define CRC_PLLE_BASE 0x0e8 +#define CRC_PLLE_MISC 0x0ec + #define CRC_RST_DEV_L_SET 0x300 #define CRC_RST_DEV_L_CACHE2 (1 << 31) #define CRC_RST_DEV_L_VCP (1 << 29) |