diff options
| author | Lucas Stach <dev@lynxeye.de> | 2013-12-03 20:56:57 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-12-04 14:59:39 +0100 |
| commit | fbe8c22a2f9bae3422b615e28ab86a0892284637 (patch) | |
| tree | 647fe7fd2e5a16fed07d8a496b012e9de978eba8 /arch/arm/mach-tegra/include/mach/tegra20-car.h | |
| parent | 7b6c063f5786b7552c2c8a97f3c57a3cd5b966a7 (diff) | |
| download | barebox-fbe8c22a2f9bae3422b615e28ab86a0892284637.tar.gz barebox-fbe8c22a2f9bae3422b615e28ab86a0892284637.tar.xz | |
tegra: switch main CPU complex to PLLX early
Running at 1GHz, rather than 13MHz certainly makes things a bit faster.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/tegra20-car.h')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/tegra20-car.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h index d4ff6fb7ba..64873d79b9 100644 --- a/arch/arm/mach-tegra/include/mach/tegra20-car.h +++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h @@ -46,6 +46,38 @@ #define CRC_CLK_OUT_ENB_L_AC97 (1 << 3) #define CRC_CLK_OUT_ENB_L_CPU (1 << 0) +#define CRC_CCLK_BURST_POLICY 0x020 +#define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT 28 +#define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ 8 +#define CRC_CCLK_BURST_POLICY_SYS_STATE_IRQ 4 +#define CRC_CCLK_BURST_POLICY_SYS_STATE_RUN 2 +#define CRC_CCLK_BURST_POLICY_SYS_STATE_IDLE 1 +#define CRC_CCLK_BURST_POLICY_SYS_STATE_STDBY 0 +#define CRC_CCLK_BURST_POLICY_FIQ_SRC_SHIFT 12 +#define CRC_CCLK_BURST_POLICY_IRQ_SRC_SHIFT 8 +#define CRC_CCLK_BURST_POLICY_RUN_SRC_SHIFT 4 +#define CRC_CCLK_BURST_POLICY_IDLE_SRC_SHIFT 0 +#define CRC_CCLK_BURST_POLICY_SRC_CLKM 0 +#define CRC_CCLK_BURST_POLICY_SRC_PLLC_OUT0 1 +#define CRC_CCLK_BURST_POLICY_SRC_CLKS 2 +#define CRC_CCLK_BURST_POLICY_SRC_PLLM_OUT0 3 +#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT0 4 +#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT4 5 +#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT3 6 +#define CRC_CCLK_BURST_POLICY_SRC_CLKD 7 +#define CRC_CCLK_BURST_POLICY_SRC_PLLX_OUT0 8 + +#define CRC_SUPER_CCLK_DIV 0x024 +#define CRC_SUPER_CDIV_ENB (1 << 31) +#define CRC_SUPER_CDIV_DIS_FROM_COP_FIQ (1 << 27) +#define CRC_SUPER_CDIV_DIS_FROM_CPU_FIQ (1 << 26) +#define CRC_SUPER_CDIV_DIS_FROM_COP_IRQ (1 << 25) +#define CRC_SUPER_CDIV_DIS_FROM_CPU_IRQ (1 << 24) +#define CRC_SUPER_CDIV_DIVIDEND_SHIFT 8 +#define CRC_SUPER_CDIV_DIVIDEND_MASK (0xff << CRC_SUPER_CDIV_DIVIDEND_SHIFT) +#define CRC_SUPER_CDIV_DIVISOR_SHIFT 0 +#define CRC_SUPER_CDIV_DIVISOR_MASK (0xff << CRC_SUPER_CDIV_DIVISOR_SHIFT) + #define CRC_SCLK_BURST_POLICY 0x028 #define CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT 28 #define CRC_SCLK_BURST_POLICY_SYS_STATE_FIQ 8 |