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authorLucas Stach <dev@lynxeye.de>2014-02-17 21:27:40 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2014-02-27 10:42:09 +0100
commit880869e55ff170cd13f1ceb0fcda57dcdffba63c (patch)
tree63a73640959ae3f3af1fdfdfcae39c218cdbdf13 /arch/arm/mach-tegra/tegra_avp_init.c
parent6350676e551000836b2fd1235a18a34a708f6eec (diff)
downloadbarebox-880869e55ff170cd13f1ceb0fcda57dcdffba63c.tar.gz
barebox-880869e55ff170cd13f1ceb0fcda57dcdffba63c.tar.xz
tegra: set AHB clock rate early
Avoids glitches in later starup phases. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra/tegra_avp_init.c')
-rw-r--r--arch/arm/mach-tegra/tegra_avp_init.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 9f8ccf3a38..4dd13306c7 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -149,6 +149,9 @@ static void start_cpu0_clocks(void)
TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY);
writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV);
+ writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
+ TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
+
/* deassert clock stop for cpu 0 */
reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;