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| author | Lucas Stach <dev@lynxeye.de> | 2014-06-03 22:34:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-06-05 08:01:14 +0200 |
| commit | c8e61fa9788f95b41f812cee99e1a1ef4ef78405 (patch) | |
| tree | 8078ba5566cc5e774fec3d8544af69fe6f7088d5 /arch/arm/mach-tegra | |
| parent | ff5f8ef49adc12bb842b451f4ad70c38dd3cc05e (diff) | |
| download | barebox-c8e61fa9788f95b41f812cee99e1a1ef4ef78405.tar.gz barebox-c8e61fa9788f95b41f812cee99e1a1ef4ef78405.tar.xz | |
tegra: lowlevel: fix ODMdata fetch on Tegra124
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/lowlevel.h | 50 |
1 files changed, 35 insertions, 15 deletions
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h index 662508a3cf..c65be0b7ba 100644 --- a/arch/arm/mach-tegra/include/mach/lowlevel.h +++ b/arch/arm/mach-tegra/include/mach/lowlevel.h @@ -31,8 +31,9 @@ /* Bootinfotable */ -#define NV_BIT_BCTSIZE 0x38 /* size of the BCT in IRAM */ -#define NV_BIT_BCTPTR 0x3C /* location of the BCT in IRAM */ +/* location of the BCT in IRAM */ +#define NV_BIT_BCTPTR_T20 0x3c +#define NV_BIT_BCTPTR_T114 0x4c /* ODM data */ #define BCT_ODMDATA_OFFSET 12 /* offset from the _end_ of the BCT */ @@ -45,19 +46,6 @@ #define T20_ODMDATA_UARTID_SHIFT 15 #define T20_ODMDATA_UARTID_MASK (7 << T20_ODMDATA_UARTID_SHIFT) -static __always_inline -u32 tegra_get_odmdata(void) -{ - u32 bctsize, bctptr, odmdata; - - bctsize = cpu_readl(TEGRA_IRAM_BASE + NV_BIT_BCTSIZE); - bctptr = cpu_readl(TEGRA_IRAM_BASE + NV_BIT_BCTPTR); - - odmdata = cpu_readl(bctptr + bctsize - BCT_ODMDATA_OFFSET); - - return odmdata; -} - /* chip ID */ #define APB_MISC_HIDREV 0x804 #define HIDREV_CHIPID_SHIFT 8 @@ -97,6 +85,38 @@ enum tegra_chiptype tegra_get_chiptype(void) } static __always_inline +u32 tegra_get_odmdata(void) +{ + u32 bctptr_offset, bctptr, odmdata_offset; + enum tegra_chiptype chiptype = tegra_get_chiptype(); + + switch(chiptype) { + case TEGRA20: + bctptr_offset = NV_BIT_BCTPTR_T20; + odmdata_offset = 4068; + break; + case TEGRA30: + bctptr_offset = NV_BIT_BCTPTR_T20; + odmdata_offset = 6116; + break; + case TEGRA114: + bctptr_offset = NV_BIT_BCTPTR_T114; + odmdata_offset = 1752; + break; + case TEGRA124: + bctptr_offset = NV_BIT_BCTPTR_T114; + odmdata_offset = 1704; + break; + default: + return 0; + } + + bctptr = cpu_readl(TEGRA_IRAM_BASE + bctptr_offset); + + return cpu_readl(bctptr + odmdata_offset); +} + +static __always_inline int tegra_get_num_cores(void) { switch (tegra_get_chiptype()) { |