ARM: zynq: move header generation to zynq_mkimage

Instead of generating a suitable image header with linker magic, move
all of this into zynq_mkimage. The configuration file format and parsing
is based on imx-image. This gets us one step further on the road to
proper multi-image support.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 63 insertions, 33 deletions

diff --git a/arch/arm/mach-zynq/include/mach/barebox.lds.h b/arch/arm/mach-zynq/include/mach/barebox.lds.h
deleted file mode 100644
index 3d35fe9880..0000000000
--- a/arch/arm/mach-zynq/include/mach/barebox.lds.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#define PRE_IMAGE \
-	.pre_image : {					\
-		. = 0x20;				\
-		KEEP(*(.flash_header_0x0*))		\
-		. = 0xa0;				\
-		KEEP(*(.ps7reg_entry_0x0A0))		\
-		. = 0x8c0;				\
-	}
diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
index 3b67e55a71..ba4b67f479 100644
--- a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
+++ b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
@@ -1,38 +1,27 @@
 #ifndef __MACH_FLASH_HEADER_H
 #define __MACH_FLASH_HEADER_H
 
-#include <asm-generic/sections.h>
+#include <stdint.h>
 
-#define __flash_header_section		__section(.flash_header_0x0)
-#define __ps7reg_entry_section		__section(.ps7reg_entry_0x0A0)
-#define __image_len_section		__section(.image_len_0x08c0)
-#define FLASH_HEADER_OFFSET		0x0
+#define REGINIT_OFFSET			0x0a0
 #define IMAGE_OFFSET			0x8c0
 
-#define DEST_BASE			0x8c0
-#define FLASH_HEADER_BASE	(DEST_BASE + FLASH_HEADER_OFFSET)
-
-struct zynq_reg_entry {
-	__le32 addr;
-	__le32 val;
-};
-
 #define WIDTH_DETECTION_MAGIC	0xAA995566
 #define IMAGE_IDENTIFICATION	0x584C4E58	/* "XLNX" */
 
 struct zynq_flash_header {
-	__le32 width_det;
-	__le32 image_id;
-	__le32 enc_stat;
-	__le32 user;
-	__le32 flash_offset;
-	__le32 length;
-	__le32 res0;
-	__le32 start_of_exec;
-	__le32 total_len;
-	__le32 res1;
-	__le32 checksum;
-	__le32 res2;
+	uint32_t width_det;
+	uint32_t image_id;
+	uint32_t enc_stat;
+	uint32_t user;
+	uint32_t flash_offset;
+	uint32_t length;
+	uint32_t res0;
+	uint32_t start_of_exec;
+	uint32_t total_len;
+	uint32_t res1;
+	uint32_t checksum;
+	uint32_t res2;
 };
 
 #endif /* __MACH_FLASH_HEADER_H */
diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h
new file mode 100644
index 0000000000..4e24064746
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h
@@ -0,0 +1,49 @@
+/*
+ * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define ZYNQ_SLCR_LOCK			0xF8000004
+#define ZYNQ_SLCR_UNLOCK		0xF8000008
+#define ZYNQ_ARM_PLL_CTRL		0xF8000100
+#define ZYNQ_DDR_PLL_CTRL		0xF8000104
+#define ZYNQ_IO_PLL_CTRL		0xF8000108
+#define ZYNQ_PLL_STATUS			0xF800010C
+#define ZYNQ_ARM_PLL_CFG		0xF8000110
+#define ZYNQ_DDR_PLL_CFG		0xF8000114
+#define ZYNQ_IO_PLL_CFG			0xF8000118
+#define ZYNQ_ARM_CLK_CTRL		0xF8000120
+#define ZYNQ_DDR_CLK_CTRL		0xF8000124
+#define ZYNQ_DCI_CLK_CTRL		0xF8000128
+#define ZYNQ_APER_CLK_CTRL		0xF800012C
+#define ZYNQ_USB0_CLK_CTRL		0xF8000130
+#define ZYNQ_USB1_CLK_CTRL		0xF8000134
+#define ZYNQ_GEM0_RCLK_CTRL		0xF8000138
+#define ZYNQ_GEM1_RCLK_CTRL		0xF800013C
+#define ZYNQ_GEM0_CLK_CTRL		0xF8000140
+#define ZYNQ_GEM1_CLK_CTRL		0xF8000144
+#define ZYNQ_SMC_CLK_CTRL		0xF8000148
+#define ZYNQ_LQSPI_CLK_CTRL		0xF800014C
+#define ZYNQ_SDIO_CLK_CTRL		0xF8000150
+#define ZYNQ_UART_CLK_CTRL		0xF8000154
+#define ZYNQ_SPI_CLK_CTRL		0xF8000158
+#define ZYNQ_CAN_CLK_CTRL		0xF800015C
+#define ZYNQ_CAN_MIOCLK_CTRL	0xF8000160
+#define ZYNQ_DBG_CLK_CTRL		0xF8000164
+#define ZYNQ_PCAP_CLK_CTRL		0xF8000168
+#define ZYNQ_TOPSW_CLK_CTRL		0xF800016C
+#define ZYNQ_FPGA0_CLK_CTRL		0xF8000170
+#define ZYNQ_FPGA1_CLK_CTRL		0xF8000180
+#define ZYNQ_FPGA2_CLK_CTRL		0xF8000190
+#define ZYNQ_FPGA3_CLK_CTRL		0xF80001A0
+#define ZYNQ_CLK_621_TRUE		0xF80001C4