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| author | Denis Orlov <denorl2009@gmail.com> | 2023-07-25 08:05:16 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-07-27 07:08:29 +0200 |
| commit | 7fb6a4535a97bfcebde42c49cd5eb4a92be4c9b9 (patch) | |
| tree | e4c19427b531a8034a8825fe58ccb7490961ebe8 /arch/mips/boot/main_entry.c | |
| parent | 96f0d255893a6fd7a3a8d37ca5713c4ebebcc843 (diff) | |
| download | barebox-7fb6a4535a97bfcebde42c49cd5eb4a92be4c9b9.tar.gz barebox-7fb6a4535a97bfcebde42c49cd5eb4a92be4c9b9.tar.xz | |
MIPS: main_entry: properly set XTLB handler for 64-bit mode
The offset of the TLB Load exception is different when 64-bit addressing
is enabled - 0x80 is used instead of 0x0. To simplify things, just copy
the handler code twice, for each of the cases.
While at it, also remove the incomprehensible cpu_has_4kex check. All of
the supported CPUs have MIPS R4K compatible exception handling scheme
(and we even hardcode that), so what are we trying to achieve there
anyway?
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Link: https://lore.barebox.org/20230725050618.3451-16-denorl2009@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/boot/main_entry.c')
| -rw-r--r-- | arch/mips/boot/main_entry.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c index 99cd2ec846..237288a337 100644 --- a/arch/mips/boot/main_entry.c +++ b/arch/mips/boot/main_entry.c @@ -50,11 +50,9 @@ static void trap_init(void) set_except_vector(i, &handle_reserved); } - if (!cpu_has_4kex) - memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); - /* FIXME: handle tlb */ memcpy((void *)(ebase), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); /* unset BOOT EXCEPTION VECTOR bit */ write_c0_status(read_c0_status() & ~ST0_BEV); |