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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2016-03-07 16:30:13 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-03-09 08:29:42 +0100 |
| commit | 5668487525cb356b356dc71799da837d0882b1ce (patch) | |
| tree | 06e3f70115e565bcd7820fda974b17216073adfc /arch/mips/include/asm/cacheops.h | |
| parent | 633caaa51ab625dd222401a9db39f17a3a8fbd5a (diff) | |
| download | barebox-5668487525cb356b356dc71799da837d0882b1ce.tar.gz barebox-5668487525cb356b356dc71799da837d0882b1ce.tar.xz | |
MIPS: pbl: import cache init code from U-Boot v2016.01-212-ga3ab2ae
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
| -rw-r--r-- | arch/mips/include/asm/cacheops.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h new file mode 100644 index 0000000000..5bd44d5fd4 --- /dev/null +++ b/arch/mips/include/asm/cacheops.h @@ -0,0 +1,29 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Most cache ops are split into a 2 bit field identifying the cache, and a 3 + * bit field identifying the cache operation. + */ +#define Cache_I 0x00 +#define Cache_D 0x01 + +#define Index_Store_Tag 0x08 + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Store_Tag_I (Cache_I | Index_Store_Tag) +#define Index_Store_Tag_D (Cache_D | Index_Store_Tag) + +#endif /* __ASM_CACHEOPS_H */ |