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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2013-10-26 13:15:06 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-10-28 09:01:48 +0100 |
| commit | 7b29868f3e4d5dbea8dfe2a2ab417301859a8f9a (patch) | |
| tree | 4b1f440f22e36f8817628734a890c3d2fea66e2f /arch/mips/include/asm/gt64120.h | |
| parent | 0ac73f13265ae1f04b58b8e4eab10fbbfb3f30b4 (diff) | |
| download | barebox-7b29868f3e4d5dbea8dfe2a2ab417301859a8f9a.tar.gz barebox-7b29868f3e4d5dbea8dfe2a2ab417301859a8f9a.tar.xz | |
MIPS: qemu-malta: use YAMON-style GT64120 memory map
There are some reasons for using YAMON-style memory map:
* we can run Linux kernel from barebox;
* we can use GXemul for running barebox.
YAMON-style GT64120 memory map make move UART to the new position.
The files gt64120.h and mach-gt64120.h are imported from Linux.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/include/asm/gt64120.h')
| -rw-r--r-- | arch/mips/include/asm/gt64120.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h new file mode 100644 index 0000000000..6b2ad0f835 --- /dev/null +++ b/arch/mips/include/asm/gt64120.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ +#ifndef _ASM_GT64120_H +#define _ASM_GT64120_H + +#define GT_DEF_BASE 0x14000000 + +/* + * Register offset addresses + */ + +/* CPU Address Decode. */ +#define GT_PCI0IOLD_OFS 0x048 +#define GT_PCI0IOHD_OFS 0x050 +#define GT_PCI0M0LD_OFS 0x058 +#define GT_PCI0M0HD_OFS 0x060 +#define GT_ISD_OFS 0x068 + +#define GT_PCI0M1LD_OFS 0x080 +#define GT_PCI0M1HD_OFS 0x088 + +#endif /* _ASM_GT64120_H */ |