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| author | Denis Orlov <denorl2009@gmail.com> | 2023-07-25 08:05:14 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-07-27 07:08:29 +0200 |
| commit | cf141b99f1e7a1a4634c177947d13fc461f84c06 (patch) | |
| tree | a810b38f3d16782fe11567885d1445b315c28aa0 /arch/mips/include/asm | |
| parent | f7bd5f1bd5294091f842d11eefa40d8c5f86d706 (diff) | |
| download | barebox-cf141b99f1e7a1a4634c177947d13fc461f84c06.tar.gz barebox-cf141b99f1e7a1a4634c177947d13fc461f84c06.tar.xz | |
MIPS: pbl: do enable 64-bit addressing in PBL
It seems more reasonable to do that in PBL code that initializes all the
other appropriate CP0 register bits. This also makes a corresponding
call in barebox proper entry code redundant, paving the way to its
removal.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Link: https://lore.barebox.org/20230725050618.3451-14-denorl2009@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/pbl_macros.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h index cc81e06a64..61e12cd004 100644 --- a/arch/mips/include/asm/pbl_macros.h +++ b/arch/mips/include/asm/pbl_macros.h @@ -175,6 +175,7 @@ copy_loop_exit: .set noreorder mips_disable_interrupts mips_disable_watchpoints + mips64_enable_64bit_addressing .set pop .endm |