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| author | Denis Orlov <denorl2009@gmail.com> | 2023-02-10 17:47:44 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-02-13 10:02:01 +0100 |
| commit | 763273ce9e2999ddc995e339bfe8d1450fb7fa7a (patch) | |
| tree | 174d5eb64d5d627a4099307af42efca604d188db /arch/mips | |
| parent | 8dd55520b761c5dc6dd3a22ed78f6e30dcabf97d (diff) | |
| download | barebox-763273ce9e2999ddc995e339bfe8d1450fb7fa7a.tar.gz barebox-763273ce9e2999ddc995e339bfe8d1450fb7fa7a.tar.xz | |
MIPS: dma: add arch-specific dma_alloc() implementation
DMA allocations should be aligned on a cache line size, at least on
cache non-coherent MIPS systems. Instead of using some hardcoded value
for an alignment from a generic implementation (which may be wrong for
us), we can get cache info from 'current_cpu_data' variable, so use it.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Link: https://lore.barebox.org/20230210144745.915720-4-denorl2009@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/dma.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index e0b4689172..49eeaac1a2 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -6,6 +6,18 @@ #ifndef __ASM_DMA_H #define __ASM_DMA_H +#include <common.h> +#include <xfuncs.h> +#include <asm/cpu-info.h> + +#define dma_alloc dma_alloc +static inline void *dma_alloc(size_t size) +{ + unsigned long max_linesz = max(current_cpu_data.dcache.linesz, + current_cpu_data.scache.linesz); + return xmemalign(max_linesz, ALIGN(size, max_linesz)); +} + #include "asm/dma-mapping.h" #endif /* __ASM_DMA_H */ |