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authorFranck Jullien <franck.jullien@gmail.com>2011-12-20 23:11:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2012-01-02 12:50:56 +0100
commit6fe9ee8eb4f85ff85b17024e25171d36c3f062ac (patch)
tree7d96bfb12aab32359d09b58eaedf591900138cc4 /arch/openrisc/Makefile
parent6449b9cff5f330de3ce0d2ebeda9aafb40877ac7 (diff)
downloadbarebox-6fe9ee8eb4f85ff85b17024e25171d36c3f062ac.tar.gz
barebox-6fe9ee8eb4f85ff85b17024e25171d36c3f062ac.tar.xz
Add OpenRISC arch
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. Even though I should have created an mach-or1200 directory, it is not necessary for now. The OpenRISC 1200 CPU is the only one available and it will be for some time. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/openrisc/Makefile')
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1 files changed, 21 insertions, 0 deletions
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
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+CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div
+
+board-$(CONFIG_GENERIC) := generic
+
+KALLSYMS += --symbol-prefix=_
+
+archprepare: maketools
+
+PHONY += maketools
+
+ifneq ($(board-y),)
+BOARD := arch/openrisc/boards/$(board-y)/
+else
+BOARD :=
+endif
+
+common-y += $(BOARD)
+common-y += arch/openrisc/lib/
+common-y += arch/openrisc/cpu/
+
+lds-y += arch/openrisc/cpu/barebox.lds