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| author | Franck Jullien <franck.jullien@gmail.com> | 2011-12-20 23:11:36 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-01-02 12:50:56 +0100 |
| commit | 6fe9ee8eb4f85ff85b17024e25171d36c3f062ac (patch) | |
| tree | 7d96bfb12aab32359d09b58eaedf591900138cc4 /arch/openrisc/lib/ashldi3.S | |
| parent | 6449b9cff5f330de3ce0d2ebeda9aafb40877ac7 (diff) | |
| download | barebox-6fe9ee8eb4f85ff85b17024e25171d36c3f062ac.tar.gz barebox-6fe9ee8eb4f85ff85b17024e25171d36c3f062ac.tar.xz | |
Add OpenRISC arch
OpenRISC is the original flagship project of the OpenCores community.
This project aims to develop a series of general purpose open source
RISC CPU architectures.
A team from OpenCores provided the first implementation, the OpenRISC
1200, written in the Verilog hardware description language.
Even though I should have created an mach-or1200 directory, it is not
necessary for now. The OpenRISC 1200 CPU is the only one available and
it will be for some time.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/openrisc/lib/ashldi3.S')
| -rw-r--r-- | arch/openrisc/lib/ashldi3.S | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/openrisc/lib/ashldi3.S b/arch/openrisc/lib/ashldi3.S new file mode 100644 index 0000000000..3e422fadc4 --- /dev/null +++ b/arch/openrisc/lib/ashldi3.S @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com> + * + * Extracted from gcc generated assembly. + * + * Extended precision shifts. + * + * R3/R4 (MSW, LSW) has 64 bit value + * R5 has shift count + * result in R11/R12 + * + */ + +.globl __ashldi3 + +__ashldi3: + l.sfeqi r5,0x0 + l.bf out /* if count = 0, go out */ + + l.addi r6,r0,0x20 /* r6 = 32 */ + l.sub r6,r6,r5 /* r6 = 32 - count */ + l.sfgtsi r6,0x0 /* if count >= 32 */ + l.bnf more_than_32 /* branch to more_than_32 */ + l.nop 0x0 + +less_than_32: + l.srl r6,r4,r6 /* r6 gets the bits moved from LSW to MSW */ + l.sll r3,r3,r5 /* shift MSW */ + l.sll r4,r4,r5 /* shift LSW */ + l.or r3,r6,r3 /* MSW gets bits shifted from LSW */ + +out: + l.ori r11,r3,0x0 + l.jr r9 + l.ori r12,r4,0x0 + +more_than_32: + l.sub r3,r0,r6 /* r3 = -r6, the number of bits above 32 */ + l.sll r3,r4,r3 /* MSW = LSW << r3 */ + l.j out /* go out */ + l.addi r4,r0,0x0 /* LSW = 0 */ |