Add OpenRISC arch

OpenRISC is the original flagship project of the OpenCores community.
This project aims to develop a series of general purpose open source
RISC CPU architectures.

A team from OpenCores provided the first implementation, the OpenRISC
1200, written in the Verilog hardware description language.

Even though I should have created an mach-or1200 directory, it is not
necessary for now. The OpenRISC 1200 CPU is the only one available and
it will be for some time.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 50 insertions, 0 deletions

diff --git a/arch/openrisc/lib/clock.c b/arch/openrisc/lib/clock.c
new file mode 100644
index 0000000000..ab0a90d4dc
--- /dev/null
+++ b/arch/openrisc/lib/clock.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <init.h>
+#include <asm/system.h>
+#include <asm/openrisc_exc.h>
+
+static uint64_t openrisc_clocksource_read(void)
+{
+	return (uint64_t)(mfspr(SPR_TTCR));
+}
+
+static struct clocksource cs = {
+	.read	= openrisc_clocksource_read,
+	.mask	= 0xffffffff,
+	.shift	= 12,
+};
+
+static int clocksource_init(void)
+{
+	mtspr(SPR_TTMR, SPR_TTMR_CR | 0xFFFFFF);
+	cs.mult = clocksource_hz2mult(OPENRISC_TIMER_FREQ, cs.shift);
+
+	init_clock(&cs);
+
+	return 0;
+}
+
+core_initcall(clocksource_init);