diff options
| author | Renaud Barbier <renaud.barbier@ge.com> | 2014-03-13 18:10:00 +0000 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-03-19 07:42:58 +0100 |
| commit | cbeded2bad56b51a2aa25151931c0de346c00707 (patch) | |
| tree | cbc4d4f896b28a44949de2028fed5b18e23a8528 /arch/ppc/ddr-8xxx/common_timing_params.h | |
| parent | 64e38721cde4d9bf6cca0b9e92a5900da1dd9577 (diff) | |
| download | barebox-cbeded2bad56b51a2aa25151931c0de346c00707.tar.gz barebox-cbeded2bad56b51a2aa25151931c0de346c00707.tar.xz | |
ppc: mpc8xxx: add DDR3 support
Add DDR3 support into the MPC8xxx DDR driver.
To avoid confusion, the function set_ddr_sdram_mode is renamed
set_ddr2_sdram_mode.
Checking for errors is simplified in the DDR2 DIMM parameters
computation to be consistent with DDR3.
This code is derived from the files found in directory drivers/ddr/fsl
from U-Boot version git-be937b5.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/ppc/ddr-8xxx/common_timing_params.h')
| -rw-r--r-- | arch/ppc/ddr-8xxx/common_timing_params.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/ppc/ddr-8xxx/common_timing_params.h b/arch/ppc/ddr-8xxx/common_timing_params.h index b2621937ea..85a1e2868f 100644 --- a/arch/ppc/ddr-8xxx/common_timing_params.h +++ b/arch/ppc/ddr-8xxx/common_timing_params.h @@ -23,6 +23,7 @@ struct common_timing_params_s { uint32_t tRRD_ps; /* maximum = 63750 ps */ uint32_t tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ uint32_t refresh_rate_ps; + uint32_t extended_op_srt; uint32_t tIS_ps; /* byte 32, spd->ca_setup */ uint32_t tIH_ps; /* byte 33, spd->ca_hold */ uint32_t tDS_ps; /* byte 34, spd->data_setup */ @@ -36,6 +37,7 @@ struct common_timing_params_s { uint32_t additive_latency; uint32_t all_DIMMs_burst_lengths_bitmask; uint32_t all_DIMMs_registered; + uint32_t all_DIMMs_unbuffered; uint32_t all_DIMMs_ECC_capable; uint64_t total_mem; uint64_t base_address; |