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| author | Renaud Barbier <renaud.barbier@ge.com> | 2012-05-17 17:49:44 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-05-17 20:33:38 +0200 |
| commit | ac28dd8620aaf23946f1e386f3f60978ffd15667 (patch) | |
| tree | ac9829314548b15da88a426a10b70eb264af4e77 /arch/ppc/include | |
| parent | 16e2a4295d57b035bcc6e501b4cdea3db596b4df (diff) | |
| download | barebox-ac28dd8620aaf23946f1e386f3f60978ffd15667.tar.gz barebox-ac28dd8620aaf23946f1e386f3f60978ffd15667.tar.xz | |
Initial e500v2 start up code
This is the first part of the start-up code. The source code origin is
U-boot and is slightly modified to have e500v2 CPU support in 32-bit
mode only.
It includes the power-up entry point, CPU initialization code and
exports definition for D-cache flush and I-cache invalidate.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/ppc/include')
| -rw-r--r-- | arch/ppc/include/asm/cache.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/ppc/include/asm/cache.h b/arch/ppc/include/asm/cache.h index 4f7ca86881..147ceb6714 100644 --- a/arch/ppc/include/asm/cache.h +++ b/arch/ppc/include/asm/cache.h @@ -31,6 +31,8 @@ extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache(void); +extern void invalidate_icache(void); #ifdef CFG_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CFG_INIT_RAM_LOCK */ |