ppc: mpc8xxx: add DDR3 support

Add DDR3 support into the MPC8xxx DDR driver.

To avoid confusion, the function set_ddr_sdram_mode is renamed
set_ddr2_sdram_mode.

Checking for errors is simplified in the DDR2 DIMM parameters
computation to be consistent with DDR3.

This code is derived from the files found in directory drivers/ddr/fsl
from U-Boot version git-be937b5.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 41 insertions, 1 deletions

diff --git a/arch/ppc/include/asm/fsl_ddr_dimm_params.h b/arch/ppc/include/asm/fsl_ddr_dimm_params.h
index 73c239be85..9e6f6b4d34 100644
--- a/arch/ppc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/ppc/include/asm/fsl_ddr_dimm_params.h
@@ -21,6 +21,8 @@ struct dimm_params_s {
 	uint32_t primary_sdram_width;
 	uint32_t ec_sdram_width;
 	uint32_t registered_dimm;
+	uint32_t device_width;
+	/* SDRAM device parameters */
 	uint32_t n_row_addr;
 	uint32_t n_col_addr;
 	uint32_t edc_config;		/* 0 = none, 1 = parity, 2 = ECC */
@@ -28,6 +30,11 @@ struct dimm_params_s {
 	uint32_t burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
 	uint32_t row_density;
 	uint64_t base_address;
+	uint32_t mirrored_dimm;
+	uint32_t mtb_ps;
+	uint32_t ftb_10th_ps;
+	uint32_t taa_ps;
+	uint32_t tfaw_ps;
 	/* SDRAM clock periods */
 	uint32_t tCKmin_X_ps;
 	uint32_t tCKmin_X_minus_1_ps;
@@ -48,6 +55,7 @@ struct dimm_params_s {
 	uint32_t tRRD_ps;	/* maximum = 63750 ps */
 	uint32_t tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 	uint32_t refresh_rate_ps;
+	uint32_t extended_op_srt;
 	uint32_t tIS_ps;	/* byte 32, spd->ca_setup */
 	uint32_t tIH_ps;	/* byte 33, spd->ca_hold */
 	uint32_t tDS_ps;	/* byte 34, spd->data_setup */
@@ -55,6 +63,7 @@ struct dimm_params_s {
 	uint32_t tRTP_ps;	/* byte 38, spd->trtp */
 	uint32_t tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
 	uint32_t tQHS_ps;	/* byte 45, spd->tqhs */
+	uint32_t rcw[16];
 };
 
 #endif
diff --git a/arch/ppc/include/asm/fsl_ddr_sdram.h b/arch/ppc/include/asm/fsl_ddr_sdram.h
index 444bcbc497..f0f3a63355 100644
--- a/arch/ppc/include/asm/fsl_ddr_sdram.h
+++ b/arch/ppc/include/asm/fsl_ddr_sdram.h
@@ -19,17 +19,24 @@
 #define SDRAM_TYPE_DDR3    7
 
 #define DDR_BL4	4
+#define DDR_BC4	DDR_BL4
+#define DDR_OTF	6
 #define DDR_BL8	8
 
 #define DDR2_RTT_OFF		0
 #define DDR2_RTT_75_OHM		1
 #define DDR2_RTT_150_OHM	2
 #define DDR2_RTT_50_OHM		3
+#define DDR3_RTT_OFF		0
+#define DDR3_RTT_40_OHM		3
 
-#if defined(CONFIG_FSL_DDR2)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
+#if defined(CONFIG_FSL_DDR2)
 typedef struct ddr2_spd_eeprom_s generic_spd_eeprom_t;
 #define FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
+#elif defined(CONFIG_FSL_DDR3)
+typedef struct ddr3_spd_eeprom_s generic_spd_eeprom_t;
+#define FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
 #endif
 
 #define FSL_DDR_ODT_NEVER		0x0
@@ -121,6 +128,10 @@ struct memctl_options_s {
 	uint32_t dynamic_power;
 	uint32_t data_bus_width;
 	uint32_t burst_length;
+	uint32_t otf_burst_chop_en;
+	uint32_t mirrored_dimm;
+	uint32_t ap_en;
+	uint32_t x4_en;
 	/* Global Timing Parameters */
 	uint32_t cas_latency_override;
 	uint32_t cas_latency_override_value;
@@ -130,16 +141,36 @@ struct memctl_options_s {
 	uint32_t clk_adjust;
 	uint32_t cpo_override;
 	uint32_t write_data_delay;
+	/* Write leveling */
+	uint32_t wrlvl_override;
+	uint32_t wrlvl_sample;
+	uint32_t wrlvl_start;
+	uint32_t wrlvl_ctl_2;
+	uint32_t wrlvl_ctl_3;
 	uint32_t half_strength_driver_enable;
 	uint32_t twoT_en;
+	uint32_t threet_en;
 	uint32_t bstopre;
 	uint32_t tCKE_clock_pulse_width_ps;
 	uint32_t tFAW_window_four_activates_ps;
 	/* Rtt impedance */
 	uint32_t rtt_override;
 	uint32_t rtt_override_value;
+	uint32_t rtt_wr_override_value;
 	/* Automatic self refresh */
 	uint32_t auto_self_refresh_en;
+	uint32_t sr_it;
+	/* ZQ calibration */
+	uint32_t zq_en;
+	/* Write leveling */
+	uint32_t wrlvl_en;
+	/* RCW override for RDIMM */
+	uint32_t rcw_override;
+	uint32_t rcw_1;
+	uint32_t rcw_2;
+	/* control register 1 */
+	uint32_t ddr_cdr1;
+	uint32_t ddr_cdr2;
 	/* read-to-write turnaround */
 	uint32_t trwt_override;
 	uint32_t trwt;