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| author | Renaud Barbier <renaud.barbier@ge.com> | 2014-03-13 18:09:58 +0000 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-03-18 17:29:06 +0100 |
| commit | df188547a95accdc26369edfdcb84cd5785f4a80 (patch) | |
| tree | 2d6a35a4e782db471606f91e3e4826475b993eac /arch/ppc/include | |
| parent | 5a6410edd7fcbd16c7c637a22a8bab7dcaeda402 (diff) | |
| download | barebox-df188547a95accdc26369edfdcb84cd5785f4a80.tar.gz barebox-df188547a95accdc26369edfdcb84cd5785f4a80.tar.xz | |
ppc: add SoC support for Freescale P1022
CPU, DDR, and LBC definitions are added to support the Freescale P1022.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/ppc/include')
| -rw-r--r-- | arch/ppc/include/asm/fsl_lbc.h | 3 | ||||
| -rw-r--r-- | arch/ppc/include/asm/processor.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/ppc/include/asm/fsl_lbc.h b/arch/ppc/include/asm/fsl_lbc.h index a59725cf3a..27d194ee74 100644 --- a/arch/ppc/include/asm/fsl_lbc.h +++ b/arch/ppc/include/asm/fsl_lbc.h @@ -25,8 +25,10 @@ #define BR_PS_8 0x00000800 /* Port Size 8 bit */ #define BR_PS_16 0x00001000 /* Port Size 16 bit */ #define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC_SHIFT 9 #define BR_V 0x00000001 #define BR_V_SHIFT 0 +#define BR_MS_FCM 0x00000020 #define BR_MS_UPMA 0x00000080 /* Convert an address into the right format for the BR registers */ @@ -61,6 +63,7 @@ #define FSL_LBC_MDR_OFFSET 0x88 #define FSL_LBC_LTESR_OFFSET 0xB0 #define FSL_LBC_LTEIR_OFFSET 0xB8 +#define FSL_LBC_LBCR_OFFSET 0xD0 #define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ #define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ diff --git a/arch/ppc/include/asm/processor.h b/arch/ppc/include/asm/processor.h index 819babb675..c9633fe507 100644 --- a/arch/ppc/include/asm/processor.h +++ b/arch/ppc/include/asm/processor.h @@ -867,6 +867,7 @@ #define SVR_8641 0x8090 #define SVR_8544 0x803401 #define SVR_8544_E 0x803C01 +#define SVR_P1022 0x80E600 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 |