RISC-V: implement cache-management errata for T-Head SoCs

Since riscv_vendor_id() can be used from pbl and non-pbl context as well
as from relocated and non-relocated code, we are able to query the
vendor id and add special vendor handlings. This is required since the
T-Head C906 and C910 implement a scheme for handling cache operations
different from the generic Zicbom extension.

While on it replace the 'asm' statement by '__asm__' so we are not
relying on GNU extension.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20221005111214.148844-5-m.felsch@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

0 files changed, 0 insertions, 0 deletions