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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-23 12:15:16 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-23 12:15:16 +0100 |
commit | ac7267ac2580590a9253549d8e129c853b6b30c7 (patch) | |
tree | 9425e0d8cfff345312da3af7e963715e776de039 /arch/riscv/include/asm/asm.h | |
parent | f4d9908504e2a35afc4f39da6aa3436903039121 (diff) | |
parent | 412806653a147177cba75fb62ea633d74c5ad1ee (diff) | |
download | barebox-ac7267ac2580590a9253549d8e129c853b6b30c7.tar.gz barebox-ac7267ac2580590a9253549d8e129c853b6b30c7.tar.xz |
Merge branch 'for-next/bthreads'
Diffstat (limited to 'arch/riscv/include/asm/asm.h')
-rw-r--r-- | arch/riscv/include/asm/asm.h | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h new file mode 100644 index 0000000000..9c992a88d8 --- /dev/null +++ b/arch/riscv/include/asm/asm.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b) __ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b) __ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define REG_SC __REG_SEL(sc.d, sc.w) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ == 8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR 8 +#define RISCV_LGPTR 3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR "8" +#define RISCV_LGPTR "3" +#endif +#elif __SIZEOF_POINTER__ == 4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR 4 +#define RISCV_LGPTR 2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR "4" +#define RISCV_LGPTR "2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ == 4) +#define RISCV_INT __ASM_STR(.word) +#define RISCV_SZINT __ASM_STR(4) +#define RISCV_LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ == 2) +#define RISCV_SHORT __ASM_STR(.half) +#define RISCV_SZSHORT __ASM_STR(2) +#define RISCV_LGSHORT __ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */ |