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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-03-13 00:25:19 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-03-18 09:03:31 +0100 |
| commit | eb1e8358f49ed6d78b5395857767296934decd3b (patch) | |
| tree | 44226736adb5fa925ee35f61ce325923a346f4fa /arch/x86 | |
| parent | d696289d6eba0b578b3a9ba506fc23cdc507b025 (diff) | |
| download | barebox-eb1e8358f49ed6d78b5395857767296934decd3b.tar.gz barebox-eb1e8358f49ed6d78b5395857767296934decd3b.tar.xz | |
usb: dwc3: Toggle GCTL.CORESOFTRESET as a first step
Toggle GCTL.CORESOFTRESET before trying to access any of the block's
registers. Without this additional step, first read of DWC3_GHWPARAMS*
that follows results in assertion of GSTS.CSRTIMEOUT and IP block
stuck in a non-functional state.
Note that all above has only been observerd on i.MX8MQ (ZII Zest
board) for USB1 controller. USB2 doesn't seem to be affected by this.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/x86')
0 files changed, 0 insertions, 0 deletions