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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-11-11 20:20:27 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-11-20 14:57:17 +0100 |
| commit | 0437a24c58ac6c0fae47cc13258942dce8bec248 (patch) | |
| tree | 215136d84dfbbe8fe9a49f554f7a8430195a1aa6 /arch | |
| parent | 2a407b25d0780fa69482b33dc832db3d54a0f230 (diff) | |
| download | barebox-0437a24c58ac6c0fae47cc13258942dce8bec248.tar.gz barebox-0437a24c58ac6c0fae47cc13258942dce8bec248.tar.xz | |
ARM: i.MX51: Setup MIPI
Setting up the MIPI unit is necessary for proper IPU support,
so set this up here. This is only needed for graphics in barebox,
the Kernel repeats this setup during booting.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx51.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index a0b627f6aa..cef302b350 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -41,11 +41,26 @@ static int imx51_silicon_revision(void) return 0; } +static void imx51_ipu_mipi_setup(void) +{ + void __iomem *hsc_addr = (void __iomem *)MX51_MIPI_HSC_BASE_ADDR; + u32 val; + + /* setup MIPI module to legacy mode */ + writel(0xf00, hsc_addr); + + /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ + val = readl(hsc_addr + 0x800); + val |= 0x30ff; + writel(val, hsc_addr + 0x800); +} + int imx51_init(void) { imx_set_silicon_revision("i.MX51", imx51_silicon_revision()); imx51_boot_save_loc((void *)MX51_SRC_BASE_ADDR); add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + imx51_ipu_mipi_setup(); return 0; } |