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| author | Jan Weitzel <j.weitzel@phytec.de> | 2012-08-14 09:04:32 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-08-14 22:01:33 +0200 |
| commit | 054085bfba59485a780a7beaf1b8744764f90cd7 (patch) | |
| tree | 8e59be9742c539ad1645efa0b6b18fa3af8d0fd0 /arch | |
| parent | d1d6369a56d275bb793743eff69dd924fe9dc0f4 (diff) | |
| download | barebox-054085bfba59485a780a7beaf1b8744764f90cd7.tar.gz barebox-054085bfba59485a780a7beaf1b8744764f90cd7.tar.xz | |
OMAP4460: ram init changes
configure Memory Adapter for 4460
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap/include/mach/omap4-silicon.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-omap/omap4_generic.c | 21 |
2 files changed, 23 insertions, 2 deletions
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h index d5517c5595..4082bac34a 100644 --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h @@ -101,6 +101,10 @@ #define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) #define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 #define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) + +/* Memory Adapter (4460 onwards) */ +#define OMAP44XX_MA_BASE 0x482AF000 + /* * Hardware Register Details */ diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index 3f6865a0ac..617d786984 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -29,6 +29,10 @@ #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 + void __noreturn reset_cpu(unsigned long addr) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); @@ -272,8 +276,7 @@ static void reset_phy(unsigned int base) void omap4_ddr_init(const struct ddr_regs *ddr_regs, const struct dpll_param *core) { - unsigned int rev; - rev = omap4_revision(); + unsigned int rev = omap4_revision(); if (rev == OMAP4430_ES2_0) { writel(0x9e9e9e9e, 0x4A100638); @@ -296,6 +299,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2); writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3); + if (rev >= OMAP4460_ES1_0) { + writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0); + + writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2); + writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3); + } + /* DDR needs to be initialised @ 19.2 MHz * So put core DPLL in bypass mode * Configure the Core DPLL but don't lock it @@ -338,6 +348,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); + if (rev >= OMAP4460_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG); + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG); + } + /* * DMM : DMM_LISA_MAP_0(Section_0) * [31:24] SYS_ADDR 0x80 |