Merge branch 'for-next/imx'

21 files changed, 239 insertions, 196 deletions

diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg
index 400a870154..9e8dce5877 100644
--- a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg
+++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg
@@ -1,3 +1,4 @@
 soc imx6
 loadaddr 0x00907000
+max_load_size 0x11000
 dcdofs 0x400
diff --git a/arch/arm/boards/guf-vincell/flash-header.imxcfg b/arch/arm/boards/guf-vincell/flash-header.imxcfg
index bb0c318b7b..8bfb5d0508 100644
--- a/arch/arm/boards/guf-vincell/flash-header.imxcfg
+++ b/arch/arm/boards/guf-vincell/flash-header.imxcfg
@@ -1,3 +1,130 @@
+loadaddr 0x71000000
 soc imx53
-loadaddr 0xf8020000
 dcdofs 0x400
+
+//=============================================================================
+//init script for i.MX53 DDR3
+//=============================================================================
+
+//=============================================================================
+// Enable all clocks (they are disabled by ROM code)
+//=============================================================================
+
+//=============================================================================
+// IOMUX
+//=============================================================================
+//DDR IO TYPE:
+wm 32	0x53fa8724 	0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+wm 32	0x53fa86fc 	0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+
+//CLOCK:
+wm 32	0x53fa8578 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+wm 32	0x53fa8570 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+
+//ADDRESS:
+wm 32	0x53fa8574 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+wm 32	0x53fa8588 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+wm 32	0x53fa86f0 	0x00300000	// IOMUXC_SW_PAD_CTL_GRP_ADDDS
+
+//Control:
+wm 32	0x53fa856c 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
+wm 32	0x53fa8580 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+wm 32	0x53fa8564 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+wm 32	0x53fa8720 	0x00300000	// IOMUXC_SW_PAD_CTL_GRP_CTLDS
+
+//Data Strobes:
+wm 32	0x53fa86f4 	0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+wm 32	0x53fa857c 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+wm 32	0x53fa8590 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+wm 32	0x53fa8568 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+wm 32	0x53fa8558 	0x00300040	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+
+//Data:
+wm 32	0x53fa8714	0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+wm 32	0x53fa8718 	0x00300000	// IOMUXC_SW_PAD_CTL_GRP_B0DS
+wm 32	0x53fa871c 	0x00300000	// IOMUXC_SW_PAD_CTL_GRP_B1DS
+wm 32	0x53fa8728 	0x00300000	// IOMUXC_SW_PAD_CTL_GRP_B2DS
+wm 32	0x53fa872c 	0x00300000	// IOMUXC_SW_PAD_CTL_GRP_B3DS
+
+wm 32	0x53fa8584 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+wm 32	0x53fa8594 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+wm 32	0x53fa8560 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+wm 32	0x53fa8554 	0x00300000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+
+
+//=============================================================================
+// DDR Controller Registers
+//=============================================================================
+// Manufacturer:	Micron
+// Device Part Number:	MT41J128M16HA-15E
+// Clock Freq.: 	400MHz
+// Density per CS in Gb: 	4
+// Chip Selects used:	1
+// Number of Banks:	8
+// Row address:    	14
+// Column address: 	10
+// Data bus width	32
+//=============================================================================
+wm 32	0x63fd901c 	0x00008000	//ESDSCR, set the Configuration request bit during MMDC set up
+
+//=============================================================================
+// Calibration setup.
+//=============================================================================
+wm 32	0x63fd9040 	0x05390003	// ZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+
+// For target board, may need to run write leveling calibration to fine tune these settings.
+wm 32	0x63fd904c 	0x00000000	//WLDECTRL0
+wm 32	0x63fd9050 	0x00000000	//WLDECTRL1
+
+////Read DQS Gating calibration
+wm 32	0x63fd907c 	0x01320135	// DGCTRL0
+wm 32	0x63fd9080 	0x01370137	// DGCTRL1
+
+//Read calibration
+wm 32	0x63fd9088 	0x3a413c3f	// RDDLCTL
+
+//Write calibration
+wm 32	0x63fd9090 	0x49434b43	// WRDLCTL
+
+// Complete calibration by forced measurement:
+wm 32	0x63fd90F8 	0x00000800	// MUR
+//=============================================================================
+// Calibration setup end
+//=============================================================================
+
+//MMDC init:
+wm 32	0x63fd9004 	0x0002002D	// ESDPDC
+wm 32	0x63fd9008 	0x00333030	// ESDOTC
+wm 32	0x63fd900c 	0x3F435333	// ESDCFG0
+wm 32	0x63fd9010 	0xB5058B63	// ESDCFG1
+wm 32	0x63fd9014 	0x01FF00DB	// ESDCFG2
+
+//MDMISC: RALAT kept to the high level of 5.
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
+//b. Small performence improvment
+wm 32	0x63fd9018 	0x00011740	// ESDMISC
+wm 32	0x63fd902c 	0x000026D2	// ESDRWD
+wm 32	0x63fd9030 	0x00430E21	// ESDOR
+wm 32	0x63fd9000 	0x83190000	// ESDCTL
+
+//Mode register writes
+wm 32	0x63fd901c 	0x02008032	// ESDSCR, MR2 write, CS0
+wm 32	0x63fd901c 	0x00008033	// ESDSCR, MR3 write, CS0
+wm 32	0x63fd901c 	0x00448031	// ESDSCR, MR1 write, CS0
+wm 32	0x63fd901c 	0x15208030	// ESDSCR, MR0write, CS0
+wm 32	0x63fd901c 	0x04008040	// ESDSCR, ZQ calibration command sent to device on CS0
+
+//wm 32	0x63fd901c 	0x0200803A	// ESDSCR, MR2 write, CS1
+//wm 32	0x63fd901c 	0x0000803B	// ESDSCR, MR3 write, CS1
+//wm 32	0x63fd901c 	0x00448039	// ESDSCR, MR1 write, CS1
+//wm 32	0x63fd901c 	0x15208038	// ESDSCR, MR0write, CS1
+//wm 32	0x63fd901c 	0x04008048	// ESDSCR, ZQ calibration command sent to device on CS1
+
+wm 32	0x63fd9020 	0x00001800	// ESDREF
+
+wm 32	0x63fd9058 	0x00033337	// ODTCTRL
+
+wm 32	0x63fd901c 	0x00000000	// MMDC0_ESDSCR, clear this register (especially the configuration bit as initialization is complete)
+
+wm 32	0x53fa8004 	0x00194005	// For TO2 only, increase LDO for VDIG_PLL to 1.3V
diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
index 0d2216f265..715e8b386f 100644
--- a/arch/arm/boards/guf-vincell/lowlevel.c
+++ b/arch/arm/boards/guf-vincell/lowlevel.c
@@ -12,130 +12,14 @@
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/cache.h>
-#include <mach/xload.h>
-
-#define IOMUX_PADCTL_DDRI_DDR (1 << 9)
-
-#define IOMUX_PADCTL_DDRDSE(x)	((x) << 19)
-#define IOMUX_PADCTL_DDRSEL(x)	((x) << 25)
-
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3		0x554
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3	0x558
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2		0x560
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1	0x564
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2	0x568
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1	0x570
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS		0x574
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0	0x578
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0	0x57c
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0	0x580
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS		0x588
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1	0x590
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1		0x594
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0		0x584
-#define IOMUXC_SW_PAD_CTL_GRP_ADDDS		0x6f0
-#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL	0x6f4
-#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE		0x6fc
-#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS		0x710
-#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE		0x714
-#define IOMUXC_SW_PAD_CTL_GRP_B0DS		0x718
-#define IOMUXC_SW_PAD_CTL_GRP_B1DS		0x71c
-#define IOMUXC_SW_PAD_CTL_GRP_CTLDS		0x720
-#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE		0x724
-#define IOMUXC_SW_PAD_CTL_GRP_B2DS		0x728
-#define IOMUXC_SW_PAD_CTL_GRP_B3DS		0x72c
-
-
-static void configure_dram_iomux(void)
-{
-	void __iomem *iomux = (void *)MX53_IOMUXC_BASE_ADDR;
-	u32 r1, r2, r4, r5, r6;
-
-	/* define the INPUT mode for DRAM_D[31:0] */
-	writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE);
-
-	/*
-	 * define the INPUT mode for SDQS[3:0]
-	 * (Freescale's documentation suggests DDR-mode for the
-	 * control line, but their source actually uses CMOS)
-	 */
-	writel(IOMUX_PADCTL_DDRI_DDR, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL);
-
-	r1 = IOMUX_PADCTL_DDRDSE(5);
-	r2 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PUE;
-	r4 = IOMUX_PADCTL_DDRSEL(2);
-	r5 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PKE | PAD_CTL_PUE | IOMUX_PADCTL_DDRI_DDR | PAD_CTL_PUS_47K_UP;
-	r6 = IOMUX_PADCTL_DDRDSE(4);
-
-	/*
-	 * this will adisable the Pull/Keeper for DRAM_x pins EXCEPT,
-	 * for DRAM_SDQS[3:0] and DRAM_SDODT[1:0]
-	 */
-	writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRPKE);
-
-	/* set global drive strength for all DRAM_x pins */
-	writel(r4, iomux + IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE);
-
-	/* set data dqs dqm drive strength */
-	writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B0DS);
-	writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0);
-	writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0);
-
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B1DS);
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1);
-	writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1);
-
-	writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B2DS);
-	writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2);
-	writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2);
-
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B3DS);
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3);
-	writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3);
-
-	/* SDCLK pad drive strength control options */
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0);
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1);
-
-	/* Control and addr bus pad drive strength control options */
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS);
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS);
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_ADDDS);
-	writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_CTLDS);
-	writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0);
-	writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1);
-
-	/*
-	 * enable hysteresis on input pins
-	 * (Freescale's documentation suggests that enable hysteresis
-	 * would be better, but their source-code doesn't)
-	 */
-	writel(PAD_CTL_HYS, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRHYS);
-}
-
-static void disable_watchdog(void)
-{
-	/*
-	 * configure WDOG to generate external reset on trigger
-	 * and disable power down counter
-	 */
-	writew(0x38, MX53_WDOG1_BASE_ADDR);
-	writew(0x0, MX53_WDOG1_BASE_ADDR + 8);
-	writew(0x38, MX53_WDOG2_BASE_ADDR);
-	writew(0x0, MX53_WDOG2_BASE_ADDR + 8);
-}
 
 extern char __dtb_imx53_guf_vincell_lt_start[];
 extern char __dtb_imx53_guf_vincell_start[];
 
-static noinline void imx53_guf_vincell_init(int is_lt)
+static noinline void imx53_guf_vincell_init(void *fdt)
 {
 	void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR;
 	void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR);
-	void *fdt;
-	u32 r;
-	enum bootsource src;
-	int instance;
 
 	arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
 
@@ -151,29 +35,10 @@ static noinline void imx53_guf_vincell_init(int is_lt)
 	pbl_set_putc(imx_uart_putc, uart);
 	pr_debug("GuF Vincell\n");
 
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (!(r > 0x70000000 && r < 0xf0000000)) {
-		disable_watchdog();
-		configure_dram_iomux();
-		imx_esdctlv4_init();
-
-		imx53_get_boot_source(&src, &instance);
-
-		if (src == BOOTSOURCE_NAND &&
-		    IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD))
-			imx53_nand_start_image();
-	}
-
-	if (is_lt)
-		fdt = __dtb_imx53_guf_vincell_lt_start;
-	else
-		fdt = __dtb_imx53_guf_vincell_start;
-
 	imx53_barebox_entry(fdt);
 }
 
-static void __imx53_guf_vincell_init(int is_lt)
+static noinline void __imx53_guf_vincell_init(void *fdt)
 {
 	arm_early_mmu_cache_invalidate();
 	imx5_cpu_lowlevel_init();
@@ -181,15 +46,19 @@ static void __imx53_guf_vincell_init(int is_lt)
 	setup_c();
 	barrier();
 
-	imx53_guf_vincell_init(is_lt);
+	imx53_guf_vincell_init(fdt);
 }
 
 ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2)
 {
-	__imx53_guf_vincell_init(1);
+	void *fdt = __dtb_imx53_guf_vincell_lt_start + get_runtime_offset();
+
+	__imx53_guf_vincell_init(fdt);
 }
 
 ENTRY_FUNCTION(start_imx53_guf_vincell, r0, r1, r2)
 {
-	__imx53_guf_vincell_init(0);
+	void *fdt = __dtb_imx53_guf_vincell_start + get_runtime_offset();
+
+	__imx53_guf_vincell_init(fdt);
 }
diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
index a12c28fceb..aff8321b9a 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
+++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
@@ -1,4 +1,5 @@
 soc imx8mq
 
 loadaddr 0x007E1000
+max_load_size 0x3F000
 dcdofs 0x400
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 05f918f6c9..9d81c278ca 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -116,4 +116,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_
 PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
 
 PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb, imx6ull_phytec_phycore_som_lc, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb, imx6ull_phytec_phycore_som, SZ_512M, false);
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index 9cedc74e07..b3da58f71f 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -74,18 +74,17 @@ static noinline void achilles_start(void)
 	arria10_start_image(barebox);
 }
 
+ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+	arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 32);
+	achilles_start();
+}
+
 ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
 {
 	void *fdt;
 
-	if (get_pc() > ARRIA10_OCRAM_ADDR) {
-		arm_cpu_lowlevel_init();
-
-		arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 32);
-
-		achilles_start();
-	}
-
 	fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
diff --git a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg
index 33621117d4..68cb08e200 100644
--- a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg
+++ b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg
@@ -1,3 +1,4 @@
 loadaddr 0x00907000
 soc imx6
+max_load_size 0x11000
 dcdofs 0x400
diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg
index 400a870154..a4abe197e4 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg
+++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg
@@ -1,3 +1,4 @@
 soc imx6
 loadaddr 0x00907000
+max_load_size 0x31000
 dcdofs 0x400
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index bf84dfa9f8..64b202b9dc 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -7,7 +7,6 @@ CONFIG_MACH_FREESCALE_MX51_PDK=y
 CONFIG_MACH_CCMX53=y
 CONFIG_MACH_FREESCALE_MX53_LOCO=y
 CONFIG_MACH_GUF_VINCELL=y
-CONFIG_MACH_GUF_VINCELL_XLOAD=y
 CONFIG_MACH_TQMA53=y
 CONFIG_MACH_FREESCALE_MX53_VMX53=y
 CONFIG_MACH_TX53=y
diff --git a/arch/arm/cpu/sections.c b/arch/arm/cpu/sections.c
index ab08ebf42e..a53236d900 100644
--- a/arch/arm/cpu/sections.c
+++ b/arch/arm/cpu/sections.c
@@ -10,4 +10,3 @@ char __bss_start[0] __attribute__((section(".__bss_start")));
 char __bss_stop[0] __attribute__((section(".__bss_stop")));
 char __image_start[0] __attribute__((section(".__image_start")));
 char __image_end[0] __attribute__((section(".__image_end")));
-uint32_t __image_end_marker[1] __attribute__((section(".__image_end_marker"))) = { 0xdeadbeef };
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 048bca0c95..be92bda4e8 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -37,6 +37,9 @@
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
 
+extern unsigned char input_data[];
+extern unsigned char input_data_end[];
+
 void __noreturn barebox_multi_pbl_start(unsigned long membase,
 		unsigned long memsize, void *boarddata)
 {
@@ -44,11 +47,11 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 	void __noreturn (*barebox)(unsigned long, unsigned long, void *);
 	unsigned long endmem = membase + memsize;
 	unsigned long barebox_base;
-	uint32_t *image_end;
-	void *pg_start;
+	void *pg_start, *pg_end;
 	unsigned long pc = get_pc();
 
-	image_end = (void *)__image_end_marker + global_variable_offset();
+	pg_start = input_data + global_variable_offset();
+	pg_end = input_data_end + global_variable_offset();
 
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
 		/*
@@ -62,14 +65,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 			relocate_to_adr(membase);
 	}
 
-	/*
-	 * image_end is the image_end_marker defined above. It is the last location
-	 * in the executable. Right after the executable the build process adds
-	 * the size of the appended compressed binary followed by the compressed
-	 * binary itself.
-	 */
-	pg_start = image_end + 2;
-	pg_len = *(image_end + 1);
+	pg_len = pg_end - pg_start;
 	uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
 
 	if (IS_ENABLED(CONFIG_RELOCATABLE))
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 503d9b18f9..c08b35a101 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -63,6 +63,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
 				imx6dl-phytec-phycore-som-nand.dtb.o \
 				imx6dl-phytec-phycore-som-emmc.dtb.o \
 				imx6ul-phytec-phycore-som.dtb.o \
+				imx6ull-phytec-phycore-som-lc.dtb.o \
 				imx6ull-phytec-phycore-som.dtb.o
 pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
 pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 73f7dbe9a6..6d1876702d 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -39,3 +39,11 @@
 &usdhc1 {
 	status = "okay";
 };
+
+&usbotg1 {
+	status = "okay";
+};
+
+&usbotg2 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 2504c9729d..d829fdd6fb 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -89,6 +89,20 @@
 	status = "disabled";
 };
 
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1>;
+	dr_mode = "otg";
+	disable-over-current;
+	status = "disabled";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "disabled";
+};
+
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -163,6 +177,12 @@
 			>;
 		};
 
+		pinctrl_usb_otg1: usbotg1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+			>;
+		};
+
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
 				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
new file mode 100644
index 0000000000..94a7830756
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+
+#include <arm/imx6ull.dtsi>
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+	model = "Phytec phyCORE-i.MX6 ULL SOM low-cost";
+	compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+&gpmi {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usdhc1 {
+	status = "okay";
+};
+
+&usbotg1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index de04132a02..4d73010131 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -39,3 +39,11 @@
 &usdhc1 {
 	status = "okay";
 };
+
+&usbotg1 {
+	status = "okay";
+};
+
+&usbotg2 {
+	status = "okay";
+};
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
index b4659256cc..8ab01f2b71 100644
--- a/arch/arm/include/asm/sections.h
+++ b/arch/arm/include/asm/sections.h
@@ -11,7 +11,6 @@ extern char __dynsym_start[];
 extern char __dynsym_end[];
 extern char __exceptions_start[];
 extern char __exceptions_stop[];
-extern uint32_t __image_end_marker[];
 
 #endif
 
diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index ddc65bbf45..53c9ce0fe6 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -36,6 +36,8 @@ SECTIONS
 {
 	. = BASE;
 
+	.image_start : { *(.__image_start) }
+
 	PRE_IMAGE
 
 	. = ALIGN(4);
@@ -91,9 +93,7 @@ SECTIONS
 	}
 	__piggydata_end = .;
 
-	. = ALIGN(4);
-	.image_end : { *(.__image_end_marker) }
-	__image_end = .;
+	.image_end : { *(.__image_end) }
 
 	_barebox_image_size = __image_end - BASE;
 	_barebox_pbl_size = __bss_start - BASE;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index edfc851138..d9b60053db 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -190,6 +190,7 @@ config ARCH_VF610
 	select ARCH_HAS_FEC_IMX
 	select CPU_V7
 	select PINCTRL
+	select OFDEVICE
 	select OFTREE
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
@@ -284,15 +285,6 @@ config MACH_GUF_VINCELL
 	bool "Garz-Fricke Vincell"
 	select ARCH_IMX53
 
-config MACH_GUF_VINCELL_XLOAD
-	depends on MACH_GUF_VINCELL
-	bool "Garz-Fricke Vincell NAND xload support"
-	help
-	  The Vincell initializes SDRAM from board code. This normally limits
-	  the image size to the size of the SoC internal SRAM. Enable this
-	  option to be able to use bigger images when booting from NAND. Images
-	  built with this option are no longer bootable from USB though.
-
 config MACH_TQMA53
 	bool "TQ i.MX53 TQMa53"
 	select ARCH_IMX53
diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h
index 05f1669318..50584bb24b 100644
--- a/arch/arm/mach-imx/include/mach/imx-header.h
+++ b/arch/arm/mach-imx/include/mach/imx-header.h
@@ -96,6 +96,7 @@ struct config_data {
 	uint32_t image_load_addr;
 	uint32_t image_dcd_offset;
 	uint32_t image_size;
+	uint32_t max_load_size;
 	uint32_t load_size;
 	char *outfile;
 	char *srkfile;
diff --git a/arch/arm/mach-imx/xload-common.c b/arch/arm/mach-imx/xload-common.c
index 13cd612d3c..c5727eba38 100644
--- a/arch/arm/mach-imx/xload-common.c
+++ b/arch/arm/mach-imx/xload-common.c
@@ -5,25 +5,6 @@
 
 int imx_image_size(void)
 {
-	uint32_t *image_end = (void *)__image_end;
-	uint32_t payload_len, pbl_len, imx_header_len, sizep;
-	void *pg_start;
-
-	pg_start = image_end + 1;
-
 	/* i.MX header is 4k */
-	imx_header_len = SZ_4K;
-
-	/* The length of the PBL image */
-	pbl_len = __image_end - _text;
-
-	sizep = 4;
-
-	/* The length of the payload is appended directly behind the PBL */
-	payload_len = *(image_end);
-
-	pr_debug("%s: payload_len: 0x%08x pbl_len: 0x%08x\n",
-			__func__, payload_len, pbl_len);
-
-	return imx_header_len + pbl_len + sizep + payload_len;
+	return barebox_image_size + SZ_4K;
 }