diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-06-11 22:36:27 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-06-11 22:36:27 +0200 |
| commit | 2bf93d1edb895287cf275782dee0ec25fce48580 (patch) | |
| tree | eef142deb46c8c66dbace250049cfc03c27a969e /arch | |
| parent | 22222b76c8592ee3bf43a4d67e2a652d533b294a (diff) | |
| parent | f0aa8a8cba8b87feb40f2d438ddcfdc50acfbd6c (diff) | |
| download | barebox-2bf93d1edb895287cf275782dee0ec25fce48580.tar.gz barebox-2bf93d1edb895287cf275782dee0ec25fce48580.tar.xz | |
Merge branch 'for-next/imx'
Diffstat (limited to 'arch')
35 files changed, 2418 insertions, 97 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 37cde0c0c5..c6a4cadb32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -353,6 +353,13 @@ menu "ARM specific settings" config ARM_OPTIMZED_STRING_FUNCTIONS bool "use assembler optimized string functions" + # + # memset() and memcpy() in arm/lib64/mem[set|cpy].S are + # written with assumption of enabled MMU and cache. Depending + # on the inputs in may fail with Alignement exception if used + # without MMU + # + depends on !CPU_V8 || MMU help Say yes here to use assembler optimized memcpy / memset functions. These functions work much faster than the normal versions but diff --git a/arch/arm/dts/imx50-kindle-common.dtsi b/arch/arm/dts/imx50-kindle-common.dtsi index 048e953898..92933e6912 100644 --- a/arch/arm/dts/imx50-kindle-common.dtsi +++ b/arch/arm/dts/imx50-kindle-common.dtsi @@ -21,19 +21,12 @@ /* this is a dummy fixed-voltage "regulator", mainly to satisfy * the esdhc implementation requiring vmmc-supply and vqmmc-supply */ - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; }; @@ -149,12 +142,12 @@ #address-cells = <1>; #size-cells = <1>; - kernel: kernel@0x41000 { + kernel: kernel@41000 { label = "kernel"; reg = <0x41000 0xe00000>; }; - diags_kernel: diags_kernel@0xe41000 { + diags_kernel: diags_kernel@e41000 { label = "diags_kernel"; reg = <0xe41000 0xe00000>; }; @@ -165,17 +158,17 @@ #address-cells = <1>; #size-cells = <1>; - imx_header: imx_header@0x400 { + imx_header: imx_header@400 { label = "imx_header"; reg = <0x400 0x800>; }; - self: self@0x1000 { + self: self@1000 { label = "self"; reg = <0x1000 0x3e000>; }; - userdata: userdata@0x3f000 { + userdata: userdata@3f000 { label = "userdata"; reg = <0x3f000 0x1400>; }; @@ -306,7 +299,7 @@ #address-cells = <1>; #size-cells = <0>; led-control = <0 0xff8 0 0>; - ledg { + ledg@2 { reg = <2>; label = "pmic_ledsg"; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/dts/imx50-kindle-d01100.dts b/arch/arm/dts/imx50-kindle-d01100.dts index 55171d7f2e..bfec71910c 100644 --- a/arch/arm/dts/imx50-kindle-d01100.dts +++ b/arch/arm/dts/imx50-kindle-d01100.dts @@ -20,10 +20,10 @@ compatible = "amazon,kindle-d01100", "fsl,imx50"; chosen { - linux,stdout-path = &uart1; + stdout-path = &uart1; }; - memory { + memory@70000000 { device_type = "memory"; reg = <0x70000000 0x10000000>; }; diff --git a/arch/arm/dts/imx50-kindle-d01200.dts b/arch/arm/dts/imx50-kindle-d01200.dts index cf65966a70..57eb9ba734 100644 --- a/arch/arm/dts/imx50-kindle-d01200.dts +++ b/arch/arm/dts/imx50-kindle-d01200.dts @@ -20,10 +20,10 @@ compatible = "amazon,kindle-d01200", "fsl,imx50"; chosen { - linux,stdout-path = &uart1; + stdout-path = &uart1; }; - memory { + memory@70000000 { device_type = "memory"; reg = <0x70000000 0x10000000>; }; diff --git a/arch/arm/dts/imx50-kindle-ey21.dts b/arch/arm/dts/imx50-kindle-ey21.dts index 3b8b5d8fcf..603f6bead6 100644 --- a/arch/arm/dts/imx50-kindle-ey21.dts +++ b/arch/arm/dts/imx50-kindle-ey21.dts @@ -20,10 +20,10 @@ compatible = "amazon,kindle-ey21", "fsl,imx50"; chosen { - linux,stdout-path = &uart1; + stdout-path = &uart1; }; - memory { + memory@70000000 { device_type = "memory"; reg = <0x70000000 0x10000000>; }; diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h new file mode 100644 index 0000000000..b94b02080a --- /dev/null +++ b/arch/arm/dts/imx8mq-pinfunc.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __DTS_IMX8MQ_PINFUNC_H +#define __DTS_IMX8MQ_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 + +#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi new file mode 100644 index 0000000000..c67438a48e --- /dev/null +++ b/arch/arm/dts/imx8mq.dtsi @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#include <dt-bindings/clock/imx8mq-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx8mq-pinfunc.h" + +/* first 128 KiB of memory are owned by ATF */ +/memreserve/ 0x40000000 0x00020000; + +/ { + /* This should really be the GPC, but we need a driver for this first */ + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + }; + + ckil: clk-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc_25m: clk-osc-25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_25m"; + }; + + osc_27m: clk-osc-27m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "osc_27m"; + }; + + clk_ext1: clk-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clk-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clk-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clk-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + interrupt-parent = <&gic>; + arm,no-tick-in-suspend; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dcss_disp0>; + }; + + peripherals@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + bus@30000000 { /* AIPS1 */ + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30000000 0x30000000 0x400000>; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mq-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp@30350000 { + compatible = "fsl,imx8mq-ocotp"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mq-anatop", "syscon"; + reg = <0x30360000 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, + <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", + "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: watchdog@30290000 { + compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: watchdog@302a0000 { + compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + }; + + bus@30400000 { /* AIPS2 */ + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30400000 0x30400000 0x400000>; + }; + + bus@30800000 { /* AIPS3 */ + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>; + + uart1: serial@30860000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, + <&clk IMX8MQ_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, + <&clk IMX8MQ_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, + <&clk IMX8MQ_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, + <&clk IMX8MQ_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx8mq-usdhc", + "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx8mq-usdhc", + "fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + bus-width = <4>; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, + <&clk IMX8MQ_CLK_ENET1_ROOT>, + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, + <&clk IMX8MQ_CLK_ENET_REF_DIV>, + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + }; + + bus@32c00000 { /* AIPS4 */ + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x32c00000 0x32c00000 0x400000>; + + hdmi: hdmi@32c00000 { + compatible = "fsl,imx8mq-hdmi"; + reg = <0x32c00000 0x33800>, /* HDP registers */ + <0x32e40000 0x40000>; /* HDP SEC register */ + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dcss_disp0_hdmi>; + }; + }; + }; + + dcss: dcss@32e00000 { + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x30000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>, + <5 IRQ_TYPE_LEVEL_HIGH>, + <6 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dpr_dc_ch0", + "dpr_dc_ch1", + "dpr_dc_ch2", + "ctx_ld", + "dtg_prg1"; + interrupt-parent = <&irqsteer_dcss>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, + <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; + clock-names = "apb", "axi", "rtrm", + "pixel", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, + <&clk IMX8MQ_CLK_DISP_AXI_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <594000000>, + <800000000>, + <400000000>, + <400000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dcss_disp0: port@0 { + reg = <0>; + dcss_disp0_hdmi: hdmi-endpoint { + remote-endpoint = <&hdmi_disp>; + }; + }; + }; + + irqsteer_dcss: interrupt-controller@32e2d000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x32e2d000 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ipg"; + nxp,channel = <2>; + nxp,endian = <1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + gpu: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x40000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, + <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, + <&clk IMX8MQ_CLK_GPU_AXI_DIV>, + <&clk IMX8MQ_CLK_GPU_AHB_DIV>; + clock-names = "core", "shader", "bus", "reg"; + + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, + <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, + <&clk IMX8MQ_CLK_GPU_AXI_SRC>, + <&clk IMX8MQ_CLK_GPU_AHB_SRC>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, + <800000000>, <800000000>; + //power-domains = <&gpu_pd>; + }; + + usb3_0: usb0@38100000 { + compatible = "fsl,imx8mq-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38100000 0x38100000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, + <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + status = "disabled"; + + usb_dwc3_0: dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0x38100000 0x10000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0 0>, <&usb3_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + //power-domains = <&usb_otg1_pd>; + snps,power-down-scale = <2>; + usb3-resume-missing-cas; + status = "disabled"; + }; + }; + + usb3_phy0: phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "usb_phy_root_clk"; + #phy-cells = <1>; + + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + }; + + usb3_1: usb1@38200000 { + compatible = "fsl,imx8mq-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38200000 0x38200000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, + <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + status = "disabled"; + + usb_dwc3_1: dwc3@38200000 { + compatible = "snps,dwc3"; + reg = <0x38200000 0x10000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy1 0>, <&usb3_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + //power-domains = <&usb_otg2_pd>; + snps,power-down-scale = <2>; + usb3-resume-missing-cas; + status = "disabled"; + }; + }; + + usb3_phy1: phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x382f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; + clock-names = "usb_phy_root_clk"; + #phy-cells = <1>; + + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x38800000 0x10000>, /* GIC Dist */ + <0x38880000 0xc0000>, /* GICR */ + <0x31000000 0x2000>, /* GICC */ + <0x31010000 0x2000>, /* GICV */ + <0x31020000 0x2000>; /* GICH */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + }; +}; diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index a68886b162..bb7e62af03 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -34,6 +34,17 @@ static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle, free(mem); } +static inline dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size, + enum dma_data_direction dir) +{ + return (dma_addr_t)ptr; +} + +static inline void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size, + enum dma_data_direction dir) +{ +} + static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size, enum dma_data_direction dir) { diff --git a/arch/arm/include/asm/syscounter.h b/arch/arm/include/asm/syscounter.h new file mode 100644 index 0000000000..a644cfaad6 --- /dev/null +++ b/arch/arm/include/asm/syscounter.h @@ -0,0 +1,24 @@ +#ifndef _ASM_SYSCNT_H_ +#define _ASM_SYSCNT_H_ + +#include <io.h> + +#define SYSCNT_CNTCR 0x0000 +#define SYSCNT_CNTCR_EN BIT(0) +#define SYSCNT_CNTCR_HDBG BIT(1) +#define SYSCNT_CNTCR_FCREQ(n) BIT(8 + (n)) + +#define SYSCNT_CNTFID(n) (0x0020 + 4 * (n)) + +static inline void syscnt_enable(void __iomem *syscnt) +{ + writel(SYSCNT_CNTCR_EN | SYSCNT_CNTCR_HDBG | SYSCNT_CNTCR_FCREQ(0), + syscnt + SYSCNT_CNTCR); +} + +static inline u32 syscnt_get_cntfrq(void __iomem *syscnt) +{ + return readl(syscnt + SYSCNT_CNTFID(0)); +} + +#endif
\ No newline at end of file diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 57c76186b4..5cf828ea36 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -77,6 +77,30 @@ static inline unsigned long read_mpidr(void) return val; } + +static inline void set_cntfrq(unsigned long cntfrq) +{ + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); +} + +static inline unsigned long get_cntfrq(void) +{ + unsigned long cntfrq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + return cntfrq; +} + +static inline unsigned long get_cntpct(void) +{ + unsigned long cntpct; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + + return cntpct; +} + #endif static inline unsigned int get_cr(void) { diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile index 77647128a5..4c0019fabe 100644 --- a/arch/arm/lib64/Makefile +++ b/arch/arm/lib64/Makefile @@ -2,7 +2,7 @@ obj-y += stacktrace.o obj-$(CONFIG_ARM_LINUX) += armlinux.o obj-y += div0.o obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o -obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o string.o extra-y += barebox.lds obj-pbl-y += runtime-offset.o diff --git a/arch/arm/lib64/memcpy.S b/arch/arm/lib64/memcpy.S index cfed3191c5..a70e96ca29 100644 --- a/arch/arm/lib64/memcpy.S +++ b/arch/arm/lib64/memcpy.S @@ -67,8 +67,8 @@ stp \ptr, \regB, [\regC], \val .endm - .weak memcpy -ENTRY(memcpy) + .weak __arch_memcpy +ENTRY(__arch_memcpy) #include "copy_template.S" ret -ENDPROC(memcpy) +ENDPROC(__arch_memcpy) diff --git a/arch/arm/lib64/memset.S b/arch/arm/lib64/memset.S index 380a54097e..d17bcc6125 100644 --- a/arch/arm/lib64/memset.S +++ b/arch/arm/lib64/memset.S @@ -54,7 +54,7 @@ tmp3w .req w9 tmp3 .req x9 .weak memset -ENTRY(memset) +ENTRY(__arch_memset) mov dst, dstin /* Preserve return value. */ and A_lw, val, #255 orr A_lw, A_lw, A_lw, lsl #8 @@ -212,4 +212,4 @@ ENTRY(memset) ands count, count, zva_bits_x b.ne .Ltail_maybe_long ret -ENDPROC(memset) +ENDPROC(__arch_memset) diff --git a/arch/arm/lib64/string.c b/arch/arm/lib64/string.c new file mode 100644 index 0000000000..cb26331527 --- /dev/null +++ b/arch/arm/lib64/string.c @@ -0,0 +1,22 @@ +#include <common.h> +#include <asm/system.h> +#include <string.h> + +void *__arch_memset(void *dst, int c, __kernel_size_t size); +void *__arch_memcpy(void * dest, const void *src, size_t count); + +void *memset(void *dst, int c, __kernel_size_t size) +{ + if (likely(get_cr() & CR_M)) + return __arch_memset(dst, c, size); + + return __default_memset(dst, c, size); +} + +void *memcpy(void * dest, const void *src, size_t count) +{ + if (likely(get_cr() & CR_M)) + return __arch_memcpy(dest, src, count); + + return __default_memcpy(dest, src, count); +}
\ No newline at end of file diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e6956acbdb..85143bd26b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -170,6 +170,15 @@ config ARCH_IMX7 select COMMON_CLK_OF_PROVIDER select ARCH_HAS_FEC_IMX +config ARCH_IMX8MQ + bool + select CPU_V8 + select PINCTRL_IMX_IOMUX_V3 + select OFTREE + select SYS_SUPPORTS_64BIT_KERNEL + select COMMON_CLK_OF_PROVIDER + select ARCH_HAS_FEC_IMX + config ARCH_VF610 bool select ARCH_HAS_L2X0 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 160ed4b084..43630282a3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -16,6 +16,7 @@ CFLAGS_imx6.o := -march=armv7-a lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o +obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_IMX_OCOTP) += ocotp.o diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index 22cf08e6ad..ab25f75b2a 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -485,7 +485,8 @@ void imx7_get_boot_source(enum bootsource *src, int *instance) */ const struct imx_boot_sw_info *info; - info = (const void *)readl(IMX_BOOT_SW_INFO_POINTER_ADDR); + info = (const void *)(unsigned long) + readl(IMX_BOOT_SW_INFO_POINTER_ADDR); if (info->boot_device_type == IMX_BOOT_SW_INFO_BDT_SD) { *src = BOOTSOURCE_MMC; @@ -623,3 +624,8 @@ void vf610_boot_save_loc(void) { imx_boot_save_loc(vf610_get_boot_source); } + +void imx8_get_boot_source(enum bootsource *src, int *instance) + __alias(imx7_get_boot_source); + +void imx8_boot_save_loc(void) __alias(imx7_boot_save_loc); diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index 6a6c4c5210..5b93d12da9 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -16,6 +16,7 @@ #include <asm/errata.h> #include <linux/types.h> +#ifdef CONFIG_CPU_32 void imx5_cpu_lowlevel_init(void) { arm_cpu_lowlevel_init(); @@ -50,3 +51,4 @@ void vf610_cpu_lowlevel_init(void) { arm_cpu_lowlevel_init(); } +#endif
\ No newline at end of file diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index d03be72487..c7375ff52a 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -490,6 +490,20 @@ int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, return __register_handler(imx_handler); } +int imx51_bbu_internal_spi_i2c_register_handler(const char *name, + char *devicefile, unsigned long flags) +{ + struct imx_internal_bbu_handler *imx_handler; + + imx_handler = __init_handler(name, devicefile, flags); + imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; + + imx_handler->flags = IMX_INTERNAL_FLAG_ERASE; + imx_handler->handler.handler = imx_bbu_internal_v1_update; + + return __register_handler(imx_handler); +} + /* * Register an i.MX53 internal boot update handler for MMC/SD */ diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 1b4c1b3df1..6fe53f3140 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -78,6 +78,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX7; if (of_machine_is_compatible("fsl,imx7d")) return IMX_CPU_IMX7; + if (of_machine_is_compatible("fsl,imx8mq")) + return IMX_CPU_IMX8MQ; if (of_machine_is_compatible("fsl,vf610")) return IMX_CPU_VF610; @@ -118,6 +120,8 @@ static int imx_init(void) ret = imx6_init(); else if (cpu_is_mx7()) ret = imx7_init(); + else if (cpu_is_mx8mq()) + ret = imx8mq_init(); else if (cpu_is_vf610()) ret = vf610_init(); else diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c index d6ff6dfc2d..f7cbc9d4ba 100644 --- a/arch/arm/mach-imx/imx50.c +++ b/arch/arm/mach-imx/imx50.c @@ -21,6 +21,7 @@ #include <mach/revision.h> #include <mach/clock-imx51_53.h> #include <mach/generic.h> +#include <mach/reset-reason.h> #define SI_REV 0x48 @@ -49,7 +50,10 @@ static int imx50_silicon_revision(void) int imx50_init(void) { + void __iomem *src = IOMEM(MX50_SRC_BASE_ADDR); + imx50_silicon_revision(); + imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons); imx53_boot_save_loc(); return 0; @@ -83,7 +87,7 @@ int imx50_devices_init(void) void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) { - void __iomem *ccm = (void __iomem *)MX50_CCM_BASE_ADDR; + void __iomem *ccm = IOMEM(MX50_CCM_BASE_ADDR); u32 r; imx5_init_lowlevel(); @@ -113,11 +117,11 @@ void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) writel(0x4, ccm + MX5_CCM_CCSR); if (cpufreq_mhz == 400) - imx5_setup_pll_400((void __iomem *)MX50_PLL1_BASE_ADDR); + imx5_setup_pll_400(IOMEM(MX50_PLL1_BASE_ADDR)); else - imx5_setup_pll_800((void __iomem *)MX50_PLL1_BASE_ADDR); + imx5_setup_pll_800(IOMEM(MX50_PLL1_BASE_ADDR)); - imx5_setup_pll_216((void __iomem *)MX50_PLL3_BASE_ADDR); + imx5_setup_pll_216(IOMEM(MX50_PLL3_BASE_ADDR)); /* Switch peripheral to PLL3 */ writel(0x00015154, ccm + MX5_CCM_CBCMR); @@ -126,7 +130,7 @@ void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) /* make sure change is effective */ while (readl(ccm + MX5_CCM_CDHIPR)); - imx5_setup_pll_400((void __iomem *)MX50_PLL2_BASE_ADDR); + imx5_setup_pll_400(IOMEM(MX50_PLL2_BASE_ADDR)); /* Switch peripheral to PLL2 */ r = 0x02800145 | diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c new file mode 100644 index 0000000000..f3246e4373 --- /dev/null +++ b/arch/arm/mach-imx/imx8mq.c @@ -0,0 +1,85 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <init.h> +#include <common.h> +#include <io.h> +#include <asm/syscounter.h> +#include <asm/system.h> +#include <mach/generic.h> +#include <mach/revision.h> +#include <mach/imx8mq-regs.h> + +#define IMX8MQ_ROM_VERSION_A0 0x800 +#define IMX8MQ_ROM_VERSION_B0 0x83C + +#define MX8MQ_ANATOP_DIGPROG 0x6c + +static void imx8mq_silicon_revision(void) +{ + void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR); + uint32_t reg = readl(anatop + MX8MQ_ANATOP_DIGPROG); + uint32_t type = (reg >> 16) & 0xff; + uint32_t rom_version; + const char *cputypestr; + + reg &= 0xff; + + if (reg == IMX_CHIP_REV_1_0) { + /* + * For B0 chip, the DIGPROG is not updated, still TO1.0. + * we have to check ROM version further + */ + rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_A0)); + if (rom_version != IMX_CHIP_REV_1_0) { + rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_B0)); + if (rom_version >= IMX_CHIP_REV_2_0) + reg = IMX_CHIP_REV_2_0; + } + } + + switch (type) { + case 0x82: + cputypestr = "i.MX8MQ"; + break; + default: + cputypestr = "unknown i.MX8M"; + break; + }; + + imx_set_silicon_revision(cputypestr, reg); +} + +static int imx8mq_init_syscnt_frequency(void) +{ + void __iomem *syscnt = IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR); + /* + * Update with accurate clock frequency + */ + set_cntfrq(syscnt_get_cntfrq(syscnt)); + syscnt_enable(syscnt); + + return 0; +} +/* + * This call needs to happen before timer driver gets probed and + * requests its update frequency via cntfrq_el0 + */ +core_initcall(imx8mq_init_syscnt_frequency); + +int imx8mq_init(void) +{ + imx8mq_silicon_revision(); + + return 0; +} diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h index 15bdbe1bec..bde3e02d27 100644 --- a/arch/arm/mach-imx/include/mach/bbu.h +++ b/arch/arm/mach-imx/include/mach/bbu.h @@ -12,6 +12,9 @@ struct imx_dcd_v2_entry; int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, unsigned long flags); +int imx51_bbu_internal_spi_i2c_register_handler(const char *name, + char *devicefile, unsigned long flags); + int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, unsigned long flags); @@ -41,6 +44,12 @@ static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char return -ENOSYS; } +static inline int imx51_bbu_internal_spi_i2c_register_handler(const char *name, + char *devicefile, unsigned long flags) +{ + return -ENOSYS; +} + static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, unsigned long flags) { diff --git a/arch/arm/mach-imx/include/mach/ccm.h b/arch/arm/mach-imx/include/mach/ccm.h new file mode 100644 index 0000000000..32254a85b4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/ccm.h @@ -0,0 +1,20 @@ +#ifndef __IMX_CCM_H__ + +/* 0 <= n <= 190 */ +#define CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) +#define CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) + +/* 0 <= n <= 120 */ +#define CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) + +#define CCM_TARGET_ROOTn_MUX(x) ((x) << 24) +#define CCM_TARGET_ROOTn_ENABLE BIT(28) + + +#define CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) +#define CCM_CCGR_SETTINGn_NOT_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b00) +#define CCM_CCGR_SETTINGn_NEEDED_RUN(n) CCM_CCGR_SETTINGn(n, 0b01) +#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) CCM_CCGR_SETTINGn(n, 0b10) +#define CCM_CCGR_SETTINGn_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b11) + +#endif
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index d54d601db0..1550e059ed 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -15,6 +15,7 @@ #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> #include <mach/imx7-regs.h> +#include <mach/imx8mq-regs.h> #include <mach/vf610-regs.h> #include <serial/imx-uart.h> @@ -47,6 +48,8 @@ #define IMX_DEBUG_SOC MX6 #elif defined CONFIG_DEBUG_IMX7D_UART #define IMX_DEBUG_SOC MX7 +#elif defined CONFIG_DEBUG_IMX8MQ_UART +#define IMX_DEBUG_SOC MX8MQ #elif defined CONFIG_DEBUG_VF610_UART #define IMX_DEBUG_SOC VF610 #else @@ -95,6 +98,13 @@ static inline void vf610_uart_setup_ll(void) lpuart_setup(base, 66000000); } +static inline void imx8_uart_setup_ll(void) +{ + void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, + CONFIG_DEBUG_IMX_UART_PORT)); + imx8mq_uart_setup(base); +} + static inline void PUTC_LL(int c) { void __iomem *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, @@ -117,6 +127,7 @@ static inline void imx53_uart_setup_ll(void) {} static inline void imx6_uart_setup_ll(void) {} static inline void imx7_uart_setup_ll(void) {} static inline void vf610_uart_setup_ll(void) {} +static inline void imx8_uart_setup_ll(void) {} #endif /* CONFIG_DEBUG_LL */ diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index ad9d9cb022..dc537941a7 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -16,6 +16,7 @@ void imx53_boot_save_loc(void); void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); void vf610_boot_save_loc(void); +void imx8_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); void imx35_get_boot_source(enum bootsource *src, int *instance); @@ -24,6 +25,7 @@ void imx53_get_boot_source(enum bootsource *src, int *instance); void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); void vf610_get_boot_source(enum bootsource *src, int *instance); +void imx8_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); int imx21_init(void); @@ -37,6 +39,7 @@ int imx53_init(void); int imx6_init(void); int imx7_init(void); int vf610_init(void); +int imx8mq_init(void); int imx1_devices_init(void); int imx21_devices_init(void); @@ -194,6 +197,18 @@ extern unsigned int __imx_cpu_type; # define cpu_is_mx7() (0) #endif +#ifdef CONFIG_ARCH_IMX8MQ +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type IMX_CPU_IMX8MQ +# endif +# define cpu_is_mx8mq() (imx_cpu_type == IMX_CPU_IMX8MQ) +#else +# define cpu_is_mx8mq() (0) +#endif + #ifdef CONFIG_ARCH_VF610 # ifdef imx_cpu_type # undef imx_cpu_type diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h index 97fe240fc4..43b9425df2 100644 --- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h @@ -1,25 +1,11 @@ #ifndef __MACH_IMX7_CCM_REGS_H__ #define __MACH_IMX7_CCM_REGS_H__ -/* 0 <= n <= 190 */ -#define CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) -#define CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) +#include "ccm.h" #define CCM_CCGR_UART1 148 #define CCM_CCGR_UART2 149 -#define CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) -#define CCM_CCGR_SETTINGn_NOT_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b00) -#define CCM_CCGR_SETTINGn_NEEDED_RUN(n) CCM_CCGR_SETTINGn(n, 0b01) -#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) CCM_CCGR_SETTINGn(n, 0b10) -#define CCM_CCGR_SETTINGn_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b11) - -/* 0 <= n <= 120 */ -#define CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) - -#define CCM_TARGET_ROOTn_MUX(x) ((x) << 24) -#define CCM_TARGET_ROOTn_ENABLE BIT(28) - #define CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128) /* diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h new file mode 100644 index 0000000000..93b584ebe2 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h @@ -0,0 +1,15 @@ +#ifndef __MACH_IMX8_CCM_REGS_H__ +#define __MACH_IMX8_CCM_REGS_H__ + +#include "ccm.h" + +#define CCM_CCGR_UART1 73 + +/* + * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad + * Applications Processor Reference Manual + */ +#define UART1_CLK_ROOT 94 +#define UART1_CLK_ROOT__25M_REF_CLK CCM_TARGET_ROOTn_MUX(0b000) + +#endif diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h new file mode 100644 index 0000000000..51936f526e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h @@ -0,0 +1,123 @@ +#ifndef __MACH_IMX8MQ_REGS_H +#define __MACH_IMX8MQ_REGS_H + +#define MX8MQ_M4_BOOTROM_BASE_ADDR 0x007E0000 + +#define MX8MQ_SAI1_BASE_ADDR 0x30010000 +#define MX8MQ_SAI6_BASE_ADDR 0x30030000 +#define MX8MQ_SAI5_BASE_ADDR 0x30040000 +#define MX8MQ_SAI4_BASE_ADDR 0x30050000 +#define MX8MQ_SPBA2_BASE_ADDR 0x300F0000 +#define MX8MQ_AIPS1_BASE_ADDR 0x301F0000 +#define MX8MQ_GPIO1_BASE_ADDR 0X30200000 +#define MX8MQ_GPIO2_BASE_ADDR 0x30210000 +#define MX8MQ_GPIO3_BASE_ADDR 0x30220000 +#define MX8MQ_GPIO4_BASE_ADDR 0x30230000 +#define MX8MQ_GPIO5_BASE_ADDR 0x30240000 +#define MX8MQ_ANA_TSENSOR_BASE_ADDR 0x30260000 +#define MX8MQ_ANA_OSC_BASE_ADDR 0x30270000 +#define MX8MQ_WDOG1_BASE_ADDR 0x30280000 +#define MX8MQ_WDOG2_BASE_ADDR 0x30290000 +#define MX8MQ_WDOG3_BASE_ADDR 0x302A0000 +#define MX8MQ_SDMA2_BASE_ADDR 0x302C0000 +#define MX8MQ_GPT1_BASE_ADDR 0x302D0000 +#define MX8MQ_GPT2_BASE_ADDR 0x302E0000 +#define MX8MQ_GPT3_BASE_ADDR 0x302F0000 +#define MX8MQ_ROMCP_BASE_ADDR 0x30310000 +#define MX8MQ_LCDIF_BASE_ADDR 0x30320000 +#define MX8MQ_IOMUXC_BASE_ADDR 0x30330000 +#define MX8MQ_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX8MQ_OCOTP_BASE_ADDR 0x30350000 +#define MX8MQ_ANATOP_BASE_ADDR 0x30360000 +#define MX8MQ_SNVS_HP_BASE_ADDR 0x30370000 +#define MX8MQ_CCM_BASE_ADDR 0x30380000 +#define MX8MQ_SRC_BASE_ADDR 0x30390000 +#define MX8MQ_GPC_BASE_ADDR 0x303A0000 +#define MX8MQ_SEMAPHORE1_BASE_ADDR 0x303B0000 +#define MX8MQ_SEMAPHORE2_BASE_ADDR 0x303C0000 +#define MX8MQ_RDC_BASE_ADDR 0x303D0000 +#define MX8MQ_CSU_BASE_ADDR 0x303E0000 + +#define MX8MQ_AIPS2_BASE_ADDR 0x305F0000 +#define MX8MQ_PWM1_BASE_ADDR 0x30660000 +#define MX8MQ_PWM2_BASE_ADDR 0x30670000 +#define MX8MQ_PWM3_BASE_ADDR 0x30680000 +#define MX8MQ_PWM4_BASE_ADDR 0x30690000 +#define MX8MQ_SYSCNT_RD_BASE_ADDR 0x306A0000 +#define MX8MQ_SYSCNT_CMP_BASE_ADDR 0x306B0000 +#define MX8MQ_SYSCNT_CTRL_BASE_ADDR 0x306C0000 +#define MX8MQ_GPT6_BASE_ADDR 0x306E0000 +#define MX8MQ_GPT5_BASE_ADDR 0x306F0000 +#define MX8MQ_GPT4_BASE_ADDR 0x30700000 +#define MX8MQ_PERFMON1_BASE_ADDR 0x307C0000 +#define MX8MQ_PERFMON2_BASE_ADDR 0x307D0000 +#define MX8MQ_QOSC_BASE_ADDR 0x307F0000 + +#define MX8MQ_SPDIF1_BASE_ADDR 0x30810000 +#define MX8MQ_ECSPI1_BASE_ADDR 0x30820000 +#define MX8MQ_ECSPI2_BASE_ADDR 0x30830000 +#define MX8MQ_ECSPI3_BASE_ADDR 0x30840000 +#define MX8MQ_UART1_BASE_ADDR 0x30860000 +#define MX8MQ_UART3_BASE_ADDR 0x30880000 +#define MX8MQ_UART2_BASE_ADDR 0x30890000 +#define MX8MQ_SPDIF2_BASE_ADDR 0x308A0000 +#define MX8MQ_SAI2_BASE_ADDR 0x308B0000 +#define MX8MQ_SAI3_BASE_ADDR 0x308C0000 +#define MX8MQ_SPBA1_BASE_ADDR 0x308F0000 +#define MX8MQ_CAAM_BASE_ADDR 0x30900000 +#define MX8MQ_AIPS3_BASE_ADDR 0x309F0000 +#define MX8MQ_MIPI_PHY_BASE_ADDR 0x30A00000 +#define MX8MQ_MIPI_DSI_BASE_ADDR 0x30A10000 +#define MX8MQ_I2C1_BASE_ADDR 0x30A20000 +#define MX8MQ_I2C2_BASE_ADDR 0x30A30000 +#define MX8MQ_I2C3_BASE_ADDR 0x30A40000 +#define MX8MQ_I2C4_BASE_ADDR 0x30A50000 +#define MX8MQ_UART4_BASE_ADDR 0x30A60000 +#define MX8MQ_MIPI_CSI_BASE_ADDR 0x30A70000 +#define MX8MQ_MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 +#define MX8MQ_CSI1_BASE_ADDR 0x30A90000 +#define MX8MQ_MU_A_BASE_ADDR 0x30AA0000 +#define MX8MQ_MU_B_BASE_ADDR 0x30AB0000 +#define MX8MQ_SEMAPHOR_HS_BASE_ADDR 0x30AC0000 +#define MX8MQ_USDHC1_BASE_ADDR 0x30B40000 +#define MX8MQ_USDHC2_BASE_ADDR 0x30B50000 +#define MX8MQ_MIPI_CS2_BASE_ADDR 0x30B60000 +#define MX8MQ_MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 +#define MX8MQ_CSI2_BASE_ADDR 0x30B80000 +#define MX8MQ_QSPI0_BASE_ADDR 0x30BB0000 +#define MX8MQ_QSPI0_AMBA_BASE 0x08000000 +#define MX8MQ_SDMA1_BASE_ADDR 0x30BD0000 +#define MX8MQ_ENET1_BASE_ADDR 0x30BE0000 + +#define MX8MQ_HDMI_CTRL_BASE_ADDR 0x32C00000 +#define MX8MQ_AIPS4_BASE_ADDR 0x32DF0000 +#define MX8MQ_DC1_BASE_ADDR 0x32E00000 +#define MX8MQ_DC2_BASE_ADDR 0x32E10000 +#define MX8MQ_DC3_BASE_ADDR 0x32E20000 +#define MX8MQ_HDMI_SEC_BASE_ADDR 0x32E40000 +#define MX8MQ_TZASC_BASE_ADDR 0x32F80000 +#define MX8MQ_MTR_BASE_ADDR 0x32FB0000 +#define MX8MQ_PLATFORM_CTRL_BASE_ADDR 0x32FE0000 + +#define MX8MQ_MXS_APBH_BASE 0x33000000 +#define MX8MQ_MXS_GPMI_BASE 0x33002000 +#define MX8MQ_MXS_BCH_BASE 0x33004000 + +#define MX8MQ_USB1_BASE_ADDR 0x38100000 +#define MX8MQ_USB2_BASE_ADDR 0x38200000 +#define MX8MQ_USB1_PHY_BASE_ADDR 0x381F0000 +#define MX8MQ_USB2_PHY_BASE_ADDR 0x382F0000 + +#define MX8MQ_MXS_LCDIF_BASE LCDIF_BASE_ADDR + +#define MX8MQ_SRC_IPS_BASE_ADDR 0x30390000 +#define MX8MQ_SRC_DDRC_RCR_ADDR 0x30391000 +#define MX8MQ_SRC_DDRC2_RCR_ADDR 0x30391004 + +#define MX8MQ_DDRC_PHY_BASE_ADDR 0x3c000000 +#define MX8MQ_DDRC_DDR_SS_GPR0 (MX8MQ_DDRC_PHY_BASE_ADDR + 0x01000000) +#define MX8MQ_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) +#define MX8MQ_DDRC_CTL_BASE_ADDR MX8MQ_DDRC_IPS_BASE_ADDR(0) +#define MX8MQ_DDR_CSD1_BASE_ADDR 0x40000000 + +#endif /* __MACH_IMX8MQ_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h index f95ef6f135..754fb9822b 100644 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h @@ -12,6 +12,7 @@ #define IMX_CPU_IMX53 53 #define IMX_CPU_IMX6 6 #define IMX_CPU_IMX7 7 +#define IMX_CPU_IMX8MQ 8 #define IMX_CPU_VF610 610 #endif /* __MACH_IMX_CPU_TYPES_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8.h b/arch/arm/mach-imx/include/mach/iomux-mx8.h new file mode 100644 index 0000000000..1caa2235b1 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx8.h @@ -0,0 +1,645 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_IOMUX_IMX8MQ_H__ +#define __MACH_IOMUX_IMX8MQ_H__ + +#include <mach/iomux-v3.h> + +#define PAD_CTL_DSE_3P3V_45_OHM 0b110 + +enum { + IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + + IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), + IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), + IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), + IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; + +static inline void mx8_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) +{ + unsigned int flags = 0; + uint32_t mode = IOMUX_MODE(pad); + + if (mode & IOMUX_CONFIG_LPSR) { + mode &= ~IOMUX_CONFIG_LPSR; + flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR; + } + + iomux_v3_setup_pad(iomux, flags, + IOMUX_CTRL_OFS(pad), + IOMUX_PAD_CTRL_OFS(pad), + IOMUX_SEL_INPUT_OFS(pad), + mode, + IOMUX_PAD_CTRL(pad), + IOMUX_SEL_INPUT(pad)); +} + +#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h index 40f6e59992..994c15c046 100644 --- a/arch/arm/mach-imx/include/mach/iomux-v3.h +++ b/arch/arm/mach-imx/include/mach/iomux-v3.h @@ -17,6 +17,7 @@ #define __MACH_IOMUX_V3_H__ #include <io.h> +#include <linux/bitfield.h> /* * build IOMUX_PAD structure @@ -95,6 +96,13 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DVS (1 << 13) #define PAD_CTL_HYS (1 << 8) +#define SHARE_CONF_PAD_CTL_DSE GENMASK(2, 0) +#define SHARE_CONF_PAD_CTL_SRE GENMASK(4, 3) + +#define SHARE_CONF_PAD_CTL_ODE BIT(5) +#define SHARE_CONF_PAD_CTL_PUE BIT(6) +#define SHARE_CONF_PAD_CTL_HYS BIT(7) + #define PAD_CTL_PKE (1 << 7) #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) #define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) @@ -118,6 +126,7 @@ typedef u64 iomux_v3_cfg_t; #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 #define IMX7_PINMUX_LPSR 0x4 +#define SHARE_CONF BIT(3) static inline void iomux_v3_setup_pad(void __iomem *iomux, unsigned int flags, u32 mux_reg, u32 conf_reg, u32 input_reg, diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h index 3898d664ef..8f141bc37e 100644 --- a/arch/arm/mach-imx/include/mach/xload.h +++ b/arch/arm/mach-imx/include/mach/xload.h @@ -4,8 +4,8 @@ int imx53_nand_start_image(void); int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len); int imx6_spi_start_image(int instance); -int imx6_esdhc_load_image(int instance, void *buf, int len); int imx6_esdhc_start_image(int instance); +int imx8_esdhc_start_image(int instance); int imx_image_size(void); diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c index e774e4e68c..08ba9b08dc 100644 --- a/arch/arm/mach-imx/xload-esdhc.c +++ b/arch/arm/mach-imx/xload-esdhc.c @@ -15,6 +15,7 @@ #include <io.h> #include <mci.h> #include <mach/imx6-regs.h> +#include <mach/imx8mq-regs.h> #include <mach/xload.h> #include <linux/sizes.h> #include "../../../drivers/mci/sdhci.h" @@ -109,8 +110,13 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data) __udelay(1); if (data) { + unsigned long dest = (unsigned long)data->dest; + + if (dest > 0xffffffff) + return -EINVAL; + /* Set up for a data transfer if we have one */ - esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest); + esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)dest); esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | SECTOR_SIZE); } @@ -211,10 +217,60 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len) return 0; } -int imx6_esdhc_load_image(int instance, void *buf, int len) +static int +esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset) +{ + void *buf = (void *)address; + u32 *ivt = buf + offset + SZ_1K; + int ret, len; + void __noreturn (*bb)(void); + unsigned int ofs; + + len = imx_image_size(); + len = ALIGN(len, SECTOR_SIZE); + + ret = esdhc_read_blocks(esdhc, buf, offset + SZ_1K + SECTOR_SIZE); + if (ret) + return ret; + + if (*(u32 *)(ivt) != 0x402000d1) { + pr_debug("IVT header not found on SD card. Found 0x%08x instead of 0x402000d1\n", + *ivt); + return -EINVAL; + } + + pr_debug("Check ok, loading image\n"); + + ret = esdhc_read_blocks(esdhc, buf, offset + len); + if (ret) { + pr_err("Loading image failed with %d\n", ret); + return ret; + } + + pr_debug("Image loaded successfully\n"); + + ofs = offset + *(ivt + 1) - *(ivt + 8); + + bb = buf + ofs; + + bb(); +} + +/** + * imx6_esdhc_start_image - Load and start an image from USDHC controller + * @instance: The USDHC controller instance (0..4) + * + * This uses esdhc_start_image() to load an image from SD/MMC. It is + * assumed that the image is the currently running barebox image (This + * information is used to calculate the length of the image). The + * image is started afterwards. + * + * Return: If successful, this function does not return. A negative error + * code is returned when this function fails. + */ +int imx6_esdhc_start_image(int instance) { struct esdhc esdhc; - int ret; switch (instance) { case 0: @@ -235,58 +291,37 @@ int imx6_esdhc_load_image(int instance, void *buf, int len) esdhc.is_mx6 = 1; - ret = esdhc_read_blocks(&esdhc, buf, len); - if (ret) - return ret; - - return 0; + return esdhc_start_image(&esdhc, 0x10000000, 0); } /** - * imx6_esdhc_start_image - Load and start an image from USDHC controller - * @instance: The USDHC controller instance (0..4) + * imx8_esdhc_start_image - Load and start an image from USDHC controller + * @instance: The USDHC controller instance (0..2) * - * This uses imx6_esdhc_load_image() to load an image from SD/MMC. - * It is assumed that the image is the currently running barebox image - * (This information is used to calculate the length of the image). The + * This uses esdhc_start_image() to load an image from SD/MMC. It is + * assumed that the image is the currently running barebox image (This + * information is used to calculate the length of the image). The * image is started afterwards. * * Return: If successful, this function does not return. A negative error * code is returned when this function fails. */ -int imx6_esdhc_start_image(int instance) +int imx8_esdhc_start_image(int instance) { - void *buf = (void *)0x10000000; - u32 *ivt = buf + SZ_1K; - int ret, len; - void __noreturn (*bb)(void); - unsigned int ofs; - - len = imx_image_size(); - len = ALIGN(len, SECTOR_SIZE); + struct esdhc esdhc; - ret = imx6_esdhc_load_image(instance, buf, 3 * SECTOR_SIZE); - if (ret) - return ret; - if (*(u32 *)(ivt) != 0x402000d1) { - pr_debug("IVT header not found on SD card. Found 0x%08x instead of 0x402000d1\n", - *ivt); + switch (instance) { + case 0: + esdhc.regs = IOMEM(MX8MQ_USDHC1_BASE_ADDR); + break; + case 1: + esdhc.regs = IOMEM(MX8MQ_USDHC2_BASE_ADDR); + break; + default: return -EINVAL; } - pr_debug("Check ok, loading image\n"); - - ret = imx6_esdhc_load_image(instance, buf, len); - if (ret) { - pr_err("Loading image failed with %d\n", ret); - return ret; - } - - pr_debug("Image loaded successfully\n"); - - ofs = *(ivt + 1) - *(ivt + 8); - - bb = buf + ofs; + esdhc.is_mx6 = 1; - bb(); -} + return esdhc_start_image(&esdhc, MX8MQ_DDR_CSD1_BASE_ADDR, SZ_32K); +}
\ No newline at end of file diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings deleted file mode 120000 index 0cecb3d080..0000000000 --- a/arch/mips/dts/include/dt-bindings +++ /dev/null @@ -1 +0,0 @@ -../../../../include/dt-bindings
\ No newline at end of file |