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authorSascha Hauer <s.hauer@pengutronix.de>2020-02-14 12:24:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-02-19 08:30:32 +0100
commit450955bc9d49e8112833e6bf8f88b51816840d1b (patch)
tree5607752ccaab079c75fbcaae41d1ce5c262fde49 /arch
parent1f33b72b9570c57590426afdd955cbb5693f1404 (diff)
downloadbarebox-450955bc9d49e8112833e6bf8f88b51816840d1b.tar.gz
Add some CCM defines for i.MX8M
This adds some clock slice indices and CCGR defines needed for the lowlevel i.MX8M code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/include/mach/imx8-ccm-regs.h25
1 files changed, 23 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
index 59d25d7..66ace0f 100644
--- a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
@@ -1,13 +1,33 @@
#ifndef __MACH_IMX8_CCM_REGS_H__
#define __MACH_IMX8_CCM_REGS_H__
-#define IMX8M_CCM_CCGR_UART1 73
+#include <mach/imx8mq-regs.h>
+
+#define IMX8M_CCM_CCGR_DDR1 5
+#define IMX8M_CCM_CCGR_I2C1 23
+#define IMX8M_CCM_CCGR_I2C2 24
+#define IMX8M_CCM_CCGR_I2C3 25
+#define IMX8M_CCM_CCGR_I2C4 26
+#define IMX8M_CCM_CCGR_SCTR 57
+#define IMX8M_CCM_CCGR_UART1 73
+#define IMX8M_CCM_CCGR_UART2 74
+#define IMX8M_CCM_CCGR_UART3 75
+#define IMX8M_CCM_CCGR_UART4 76
+#define IMX8M_CCM_CCGR_GIC 92
/*
* Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad
* Applications Processor Reference Manual
*/
+#define IMX8M_ARM_A53_CLK_ROOT 0
+#define IMX8M_DRAM_SEL_CFG 48
+#define IMX8M_DRAM_ALT_CLK_ROOT 64
+#define IMX8M_DRAM_APB_CLK_ROOT 65
#define IMX8M_UART1_CLK_ROOT 94
+#define IMX8M_UART2_CLK_ROOT 95
+#define IMX8M_UART3_CLK_ROOT 96
+#define IMX8M_UART4_CLK_ROOT 97
+#define IMX8M_GIC_CLK_ROOT 100
#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000)
/* 0 <= n <= 190 */
@@ -17,10 +37,11 @@
/* 0 <= n <= 120 */
#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n))
+#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f)
+#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000)
#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24)
#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28)
-
#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4))
#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00)
#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01)