Merge branch 'for-next/ppc'

Conflicts:
	arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
	arch/ppc/configs/p2020rdb_defconfig
	arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h

6 files changed, 108 insertions, 0 deletions

diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index c5fae0d7aa..2431cb5d37 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -35,6 +35,7 @@
 #include <mach/mpc85xx.h>
 #include <mach/mmu.h>
 #include <mach/immap_85xx.h>
+#include <mach/gianfar.h>
 #include <mach/clock.h>
 #include <mach/early_udelay.h>
 
@@ -62,6 +63,15 @@
 #define SYSCLK_50	50000000
 #define SYSCLK_100	100000000
 
+/* Ethernet. Use eTSEC3 */
+static struct gfar_info_struct gfar_info[] = {
+	{
+		.phyaddr = 1,
+		.tbiana = 0,
+		.tbicr = 0,
+	},
+};
+
 /* I2C busses. */
 struct i2c_platform_data i2cplat = {
 	.bitrate = 400000,
@@ -76,6 +86,9 @@ static int devices_init(void)
 	add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
 			0x100, IORESOURCE_MEM, &i2cplat);
 
+	/* eTSEC3 */
+	fsl_eth_init(3, &gfar_info[0]);
+
 	devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
 			    "self0");
 	return 0;
diff --git a/arch/ppc/configs/p2020rdb_defconfig b/arch/ppc/configs/p2020rdb_defconfig
index c040635e70..7690327424 100644
--- a/arch/ppc/configs/p2020rdb_defconfig
+++ b/arch/ppc/configs/p2020rdb_defconfig
@@ -21,6 +21,12 @@ CONFIG_MALLOC_SIZE=0x200000
 CONFIG_BAUDRATE=115200
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_RELOCATABLE=y
+CONFIG_DRIVER_NET_GIANFAR=y
+CONFIG_NET=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_PING=y
+CONFIG_TFTP=y
 CONFIG_I2C=y
 CONFIG_I2C_IMX=y
 CONFIG_CMD_I2C=y
diff --git a/arch/ppc/mach-mpc85xx/Makefile b/arch/ppc/mach-mpc85xx/Makefile
index 03addaf47b..af9be29271 100644
--- a/arch/ppc/mach-mpc85xx/Makefile
+++ b/arch/ppc/mach-mpc85xx/Makefile
@@ -6,3 +6,4 @@ obj-y			+= fsl_law.o
 obj-y			+= speed.o
 obj-y			+=time.o
 obj-$(CONFIG_MP)	+= mp.o
+obj-$(CONFIG_DRIVER_NET_GIANFAR) += eth-devices.o
diff --git a/arch/ppc/mach-mpc85xx/eth-devices.c b/arch/ppc/mach-mpc85xx/eth-devices.c
new file mode 100644
index 0000000000..02a3722136
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/eth-devices.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <mach/immap_85xx.h>
+#include <mach/gianfar.h>
+
+int fsl_eth_init(int num, struct gfar_info_struct *gf)
+{
+	struct resource *res;
+
+	res = xzalloc(3 * sizeof(struct resource));
+	/* TSEC interface registers */
+	res[0].start = GFAR_BASE_ADDR + ((num - 1) * 0x1000);
+	res[0].end = res[0].start + 0x1000;
+	res[0].flags = IORESOURCE_MEM;
+	/* External PHY access always through eTSEC1 */
+	res[1].start = MDIO_BASE_ADDR;
+	res[1].end = res[1].start + 0x1000;
+	res[1].flags = IORESOURCE_MEM;
+	/* Access to TBI/RTBI interface. */
+	res[2].start = MDIO_BASE_ADDR + ((num - 1) * 0x1000);
+	res[2].end = res[2].start + 0x1000;
+	res[2].flags = IORESOURCE_MEM;
+
+	add_generic_device_res("gfar", DEVICE_ID_DYNAMIC, res, 3, gf);
+
+	return 0;
+}
diff --git a/arch/ppc/mach-mpc85xx/include/mach/gianfar.h b/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
new file mode 100644
index 0000000000..ae3163865c
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2004, 2007, 2009  Freescale Semiconductor, Inc.
+ * (C) Copyright 2003, Motorola, Inc.
+ * based on tsec.h by Xianghua Xiao and Andy Fleming 2003-2009
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Platform data for the Motorola Triple Speed Ethernet Controller
+ */
+
+struct gfar_info_struct {
+	unsigned int phyaddr;
+	unsigned int tbiana;
+	unsigned int tbicr;
+};
+
+int fsl_eth_init(int num, struct gfar_info_struct *gf);
diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
index b686a09b6a..cd43023259 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
@@ -39,6 +39,11 @@
 
 #define MPC85xx_GPIO_OFFSET	0xf000
 #define MPC85xx_L2_OFFSET	0x20000
+#ifdef CONFIG_TSECV2
+#define TSEC1_OFFSET		0xB0000
+#else
+#define TSEC1_OFFSET		0x24000
+#endif
 
 #define MPC85xx_PIC_OFFSET	0x40000
 #define MPC85xx_GUTS_OFFSET	0xe0000
@@ -129,6 +134,9 @@
 #define		MPC85xx_DEVDISR_TB1	0x00001000
 #define MPC85xx_GUTS_RSTCR_OFFSET	0xb0
 
+#define GFAR_BASE_ADDR		(CFG_IMMR + TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CFG_IMMR + 0x24000)
+
 #define I2C1_BASE_ADDR		(CFG_IMMR + 0x3000)
 #define I2C2_BASE_ADDR		(CFG_IMMR + 0x3100)