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author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-06-02 16:28:34 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-06-02 16:28:34 +0200 |
commit | 7925ab2d727ed489fe6c8a8aac7703bfe0a06ea2 (patch) | |
tree | d8a6b2ed6cbca31842577f6ebf26852fac4e872a /arch | |
parent | 07bdbf9c6d41a1de74f562bc52b94d0dfe68b90f (diff) | |
parent | ea444c2f2c469ff5769de28e07a1814fe2a16e42 (diff) | |
download | barebox-7925ab2d727ed489fe6c8a8aac7703bfe0a06ea2.tar.gz barebox-7925ab2d727ed489fe6c8a8aac7703bfe0a06ea2.tar.xz |
Merge branch 'for-next/tegra'
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/configs/tegra20_colibri_iris_defconfig | 24 | ||||
-rw-r--r-- | arch/arm/dts/tegra20-colibri-iris.dts | 32 | ||||
-rw-r--r-- | arch/arm/dts/tegra20-colibri.dtsi | 190 | ||||
-rw-r--r-- | arch/arm/dts/tegra20-paz00.dts | 216 | ||||
-rw-r--r-- | arch/arm/dts/tegra20.dtsi | 8 | ||||
-rw-r--r-- | arch/arm/mach-tegra/Kconfig | 13 |
6 files changed, 483 insertions, 0 deletions
diff --git a/arch/arm/configs/tegra20_colibri_iris_defconfig b/arch/arm/configs/tegra20_colibri_iris_defconfig new file mode 100644 index 0000000000..37a0e8ac51 --- /dev/null +++ b/arch/arm/configs/tegra20_colibri_iris_defconfig @@ -0,0 +1,24 @@ +CONFIG_BUILTIN_DTB_NAME="tegra20-colibri-iris" +CONFIG_ARCH_TEGRA=y +CONFIG_AEABI=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_STACK_SIZE=0x10000 +CONFIG_MALLOC_SIZE=0x4000000 +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_GLOB_SORT=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_HUSH_GETOPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_RESET=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CLK=y +CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/dts/tegra20-colibri-iris.dts b/arch/arm/dts/tegra20-colibri-iris.dts new file mode 100644 index 0000000000..804750e421 --- /dev/null +++ b/arch/arm/dts/tegra20-colibri-iris.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +/include/ "tegra20-colibri.dtsi" + +/ { + model = "Toradex Colibri T20 on Iris"; + compatible = "toradex,iris", "toradex,colibri-t20", "nvidia,tegra20"; + + pinmux { + state_default: pinmux { + hdint { + nvidia,tristate = <0>; + }; + + i2cddc { + nvidia,tristate = <0>; + }; + + sdio4 { + nvidia,tristate = <0>; + }; + + uarta { + nvidia,tristate = <0>; + }; + + uartd { + nvidia,tristate = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra20-colibri.dtsi b/arch/arm/dts/tegra20-colibri.dtsi new file mode 100644 index 0000000000..3644e7de4e --- /dev/null +++ b/arch/arm/dts/tegra20-colibri.dtsi @@ -0,0 +1,190 @@ +/include/ "tegra20.dtsi" + +/ { + model = "Toradex Colibri T20"; + compatible = "toradex,colibri_t20", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + audio_refclk { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + crt { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + displaya { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", "ld8", + "ld9", "ld10", "ld11", "ld12", "ld13", + "ld14", "ld15", "ld16", "ld17", + "lhs", "lpw0", "lpw2", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvs"; + nvidia,function = "displaya"; + nvidia,tristate = <1>; + }; + gpio_dte { + nvidia,pins = "dte"; + nvidia,function = "rsvd1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + gpio_gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "dap1", "dap2", "dap4", "gpu", "irrx", + "irtx", "spia", "spib", "spic"; + nvidia,function = "gmi"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + gpio_pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + gpio_uac { + nvidia,pins = "uac"; + nvidia,function = "rsvd2"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + nvidia,tristate = <1>; + }; + i2c1 { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + i2cddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + irda { + nvidia,pins = "uad"; + nvidia,function = "irda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + nand { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "nand"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + nvidia,tristate = <0>; + }; + pwm { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + nvidia,tristate = <1>; + }; + sdio4 { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + spi4 { + nvidia,pins = "slxa", "slxc", "slxd", "slxk"; + nvidia,function = "spi4"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + uarta { + nvidia,pins = "sdio1"; + nvidia,function = "uarta"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + uartd { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + ulpi { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + ulpi_refclk { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + usb_gpio { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + vi { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,function = "vi"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + vi_sc { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 09ccb8ba3a..e8486aae49 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -9,4 +9,220 @@ memory { reg = <0x00000000 0x20000000>; }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atc", "atd", "ate", + "dap2", "gmb", "gmc", "gmd", "spia", + "spib", "spic", "spid", "spie"; + nvidia,function = "gmi"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "pllc_out1"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gpu { + nvidia,pins = "gpu", "sdb", "sdd"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + kbcb { + nvidia,pins = "kbcb", "kbcd"; + nvidia,function = "sdio2"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdc { + nvidia,pins = "sdc"; + nvidia,function = "twc"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spi4"; + }; + spdi { + nvidia,pins = "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + spif { + nvidia,pins = "spif", "uac"; + nvidia,function = "rsvd4"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "spdif"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dap2", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", + "gpu", "gpu7", "gpv", "i2cp", "pta", + "rm", "sdio1", "slxk", "spdo", "uac", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap3", "dap4", "dtb", + "dtc", "dte", "slxa", "slxc", "slxd", + "spdi"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_csus { + nvidia,pins = "csus", "spia", "spib", "spid", + "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "irrx", "irtx", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "spic", "spig", "uaa", "uab"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_dta { + nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", + "spie", "spih", "uad", "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_hdint { + nvidia,pins = "hdint", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhs", "lsc0", "lspi", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_lcsn { + nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", + "lm0", "lm1", "lpp", "lpw0", "lpw1", + "lpw2", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "lvp1", "sdb"; + nvidia,tristate = <1>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index b7d1e27de2..f63ead89db 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -34,6 +34,14 @@ interrupt-controller; }; + pinmux: pinmux { + compatible = "nvidia,tegra20-pinmux"; + reg = <0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8>; /* Pad control registers */ + }; + pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 965e7ab6ba..9224e628cb 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -5,6 +5,7 @@ choice config ARCH_TEGRA_2x_SOC bool "Tegra 20" + select PINCTRL_TEGRA20 endchoice @@ -52,6 +53,11 @@ config ARCH_TEXT_BASE choice prompt "Tegra 20 Board Type" +config MACH_TEGRA20_GENERIC + bool "Generic DT based board" + help + Say Y here if you are building for a generic DT based board. + config MACH_TOSHIBA_AC100 bool "Toshiba AC100" help @@ -59,6 +65,13 @@ config MACH_TOSHIBA_AC100 endchoice +if MACH_TEGRA20_GENERIC + +config BOARDINFO + default "Generic Tegra20 board" + +endif #MACH_TEGRA20_GENERIC + source arch/arm/boards/toshiba-ac100/Kconfig endif #ARCH_TEGRA_2x_SOC |