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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-08-12 15:21:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-08-13 20:27:38 +0200 |
| commit | 837795895801e6c368a564f9dcbbda2c87137ea7 (patch) | |
| tree | 632621b6a35fdb86042157ca392e42a6e1875b84 /arch | |
| parent | e4e141159d5019006a85d4be5fb672a7e928dc38 (diff) | |
| download | barebox-837795895801e6c368a564f9dcbbda2c87137ea7.tar.gz barebox-837795895801e6c368a564f9dcbbda2c87137ea7.tar.xz | |
ARM __mmu_cache_*: Do not clobber registers
Save/restore the registers used in __mmu_cache_* so that they can
be called as regular C functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/cache-armv4.S | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/cache-armv7.S | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S index 2231eee06b..22fab1455c 100644 --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -46,6 +46,7 @@ ENDPROC(__mmu_cache_off) .section .text.__mmu_cache_flush ENTRY(__mmu_cache_flush) + stmfd sp!, {r6, r11, lr} mrc p15, 0, r6, c0, c0 @ get processor ID mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size @@ -74,7 +75,7 @@ no_cache_id: mcr p15, 0, r1, c7, c5, 0 @ flush I cache mcr p15, 0, r1, c7, c6, 0 @ flush D cache mcr p15, 0, r1, c7, c10, 4 @ drain WB - mov pc, lr + ldmfd sp!, {r6, r11, pc} ENDPROC(__mmu_cache_flush) /* diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 9bd74254f3..2eba959672 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -3,6 +3,7 @@ .section .text.__mmu_cache_on ENTRY(__mmu_cache_on) + stmfd sp!, {r11, lr} mov r12, lr #ifdef CONFIG_MMU mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 @@ -28,7 +29,7 @@ ENTRY(__mmu_cache_on) mrc p15, 0, r0, c1, c0, 0 @ and read it back mov r0, #0 mcr p15, 0, r0, c7, c5, 4 @ ISB - mov pc, r12 + ldmfd sp!, {r11, pc} ENDPROC(__mmu_cache_on) .section .text.__mmu_cache_off @@ -54,6 +55,7 @@ ENDPROC(__mmu_cache_off) .section .text.__mmu_cache_flush ENTRY(__mmu_cache_flush) + stmfd sp!, {r10, lr} mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) mov r10, #0 @@ -111,7 +113,7 @@ iflush: mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 4 @ ISB - mov pc, lr + ldmfd sp!, {r10, pc} ENDPROC(__mmu_cache_flush) /* |