Rename remainings structs and functions from mc13892_ to mc13xxx_

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 46 insertions, 46 deletions

diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index fa6be1a1ed..a76f09f208 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -353,33 +353,33 @@ static int f3s_core_init(void)
 
 core_initcall(f3s_core_init);
 
-static int f3s_get_rev(struct mc13892 *mc13892)
+static int f3s_get_rev(struct mc13xxx *mc13xxx)
 {
 	u32 rev;
 	int err;
 
-	err = mc13892_reg_read(mc13892, MC13892_REG_IDENTIFICATION, &rev);
+	err = mc13xxx_reg_read(mc13xxx, MC13892_REG_IDENTIFICATION, &rev);
 	if (err)
 		return err;
 
-	dev_info(&mc13892->client->dev, "revision: 0x%x\n", rev);
+	dev_info(&mc13xxx->client->dev, "revision: 0x%x\n", rev);
 	if (rev == 0x00ffffff)
 		return -ENODEV;
 
 	return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1;
 }
 
-static int f3s_pmic_init_v2(struct mc13892 *mc13892)
+static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx)
 {
 	int err = 0;
 
 	/* COMPARE pin (GPIO1_5) as output and set high */
 	gpio_direction_output( 32*0 + 5 , 1);
 
-	err |= mc13892_set_bits(mc13892, MC13892_REG_SETTING_0, 0x03, 0x03);
-	err |= mc13892_set_bits(mc13892, MC13892_REG_MODE_0, 0x01, 0x01);
+	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03);
+	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01);
 	if (err)
-		dev_err(&mc13892->client->dev,
+		dev_err(&mc13xxx->client->dev,
 			"Init sequence failed, the system might not be working!\n");
 
 	return err;
@@ -404,22 +404,22 @@ static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
 
 static int f3s_pmic_init(void)
 {
-	struct mc13892 *mc13892;
+	struct mc13xxx *mc13xxx;
 	struct mc9sdz60 *mc9sdz60;
 	int rev;
 
-	mc13892 = mc13892_get();
-	if (!mc13892) {
-		printf("FAILED to get mc13xxx handle!\n");
+	mc13xxx = mc13xxx_get();
+	if (!mc13xxx) {
+		printf("FAILED to get PMIC handle!\n");
 		return 0;
 	}
 
-	rev = f3s_get_rev(mc13892);
+	rev = f3s_get_rev(mc13xxx);
 	switch (rev) {
 	case MX35PDK_BOARD_REV_1:
 		break;
 	case MX35PDK_BOARD_REV_2:
-		f3s_pmic_init_v2(mc13892);
+		f3s_pmic_init_v2(mc13xxx);
 		break;
 	default:
 		printf("FAILED to identify board revision!\n");
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index c616a87184..63c89b76e5 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -121,101 +121,101 @@ static const struct spi_board_info mx51_babbage_spi_board_info[] = {
 
 static void babbage_power_init(void)
 {
-	struct mc13892 *mc13892;
+	struct mc13xxx *mc13xxx;
 	u32 val;
 
-	mc13892 = mc13892_get();
-	if (!mc13892) {
-		printf("could not get mc13892\n");
+	mc13xxx = mc13xxx_get();
+	if (!mc13xxx) {
+		printf("could not get PMIC\n");
 		return;
 	}
 
 	/* Write needed to Power Gate 2 register */
-	mc13892_reg_read(mc13892, MC13892_REG_POWER_MISC, &val);
+	mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
 	val &= ~0x10000;
-	mc13892_reg_write(mc13892, MC13892_REG_POWER_MISC, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
 
 	/* Write needed to update Charger 0 */
-	mc13892_reg_write(mc13892, MC13892_REG_CHARGE, 0x0023807F);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F);
 
 	/* power up the system first */
-	mc13892_reg_write(mc13892, MC13892_REG_POWER_MISC, 0x00200000);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000);
 
 	if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
 		/* Set core voltage to 1.1V */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_0, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
 		val &= ~0x1f;
 		val |= 0x14;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_0, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
 
 		/* Setup VCC (SW2) to 1.25 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_1, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
 		val &= ~0x1f;
 		val |= 0x1a;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_1, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
 
 		/* Setup 1V2_DIG1 (SW3) to 1.25 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_2, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
 		val &= ~0x1f;
 		val |= 0x1a;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_2, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
 	} else {
 		/* Setup VCC (SW2) to 1.225 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_1, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
 		val &= ~0x1f;
 		val |= 0x19;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_1, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
 
 		/* Setup 1V2_DIG1 (SW3) to 1.2 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_2, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
 		val &= ~0x1f;
 		val |= 0x18;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_2, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
 	}
 
-	if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) {
+	if (mc13xxx_get_revision(mc13xxx) < MC13892_REVISION_2_0) {
 		/* Set switchers in PWM mode for Atlas 2.0 and lower */
 		/* Setup the switcher mode for SW1 & SW2*/
-		mc13892_reg_read(mc13892, MC13892_REG_SW_4, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
 		val &= ~0x3c0f;
 		val |= 0x1405;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_4, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
 
 		/* Setup the switcher mode for SW3 & SW4 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_5, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
 		val &= ~0xf0f;
 		val |= 0x505;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_5, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
 	} else {
 		/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
 		/* Setup the switcher mode for SW1 & SW2*/
-		mc13892_reg_read(mc13892, MC13892_REG_SW_4, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
 		val &= ~0x3c0f;
 		val |= 0x2008;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_4, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
 
 		/* Setup the switcher mode for SW3 & SW4 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_5, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
 		val &= ~0xf0f;
 		val |= 0x808;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_5, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
 	}
 
 	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
-	mc13892_reg_read(mc13892, MC13892_REG_SETTING_0, &val);
+	mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
 	val &= ~0x34030;
 	val |= 0x10020;
-	mc13892_reg_write(mc13892, MC13892_REG_SETTING_0, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
 
 	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
-	mc13892_reg_read(mc13892, MC13892_REG_SETTING_1, &val);
+	mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val);
 	val &= ~0x1FC;
 	val |= 0x1F4;
-	mc13892_reg_write(mc13892, MC13892_REG_SETTING_1, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
 
 	/* Configure VGEN3 and VCAM regulators to use external PNP */
 	val = 0x208;
-	mc13892_reg_write(mc13892, MC13892_REG_MODE_1, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
 	udelay(200);
 #define GPIO_LAN8700_RESET	(1 * 32 + 14)
 
@@ -224,7 +224,7 @@ static void babbage_power_init(void)
 
 	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 	val = 0x49249;
-	mc13892_reg_write(mc13892, MC13892_REG_MODE_1, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
 
 	udelay(500);