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author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-04-27 22:23:09 +0200 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-05-17 08:29:42 +0200 |
commit | 9174376cd08e1e3e638cd852525cc529d25fde47 (patch) | |
tree | 7823355296ac9f2acf5c9ff6ad4dad21722260b3 /arch | |
parent | 109a9487f5565e798129e69b6a8fc53b083be470 (diff) | |
download | barebox-9174376cd08e1e3e638cd852525cc529d25fde47.tar.gz barebox-9174376cd08e1e3e638cd852525cc529d25fde47.tar.xz |
RISC-V: sifive: add HiFive board support
With the recently added SiFive support, we now have enough functionality
to boot a HiFive board to shell:
qemu-system-riscv64 -M sifive_u serial_stdio \
-kernel./images/barebox-hifive-unleashed.img
Some more drivers need to be ported for this to be useful:
- sifive,spi0 needed for talking to SD-Card
- clocksource The riscv-timer seems to be 10x too fast
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210427202309.32077-12-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv/Kconfig.socs | 19 | ||||
-rw-r--r-- | arch/riscv/boards/Makefile | 1 | ||||
-rw-r--r-- | arch/riscv/boards/hifive/Makefile | 3 | ||||
-rw-r--r-- | arch/riscv/boards/hifive/lowlevel.c | 25 | ||||
-rw-r--r-- | arch/riscv/configs/sifive_defconfig | 128 | ||||
-rw-r--r-- | arch/riscv/dts/Makefile | 2 | ||||
-rw-r--r-- | arch/riscv/dts/hifive-unleashed-a00.dts | 3 | ||||
-rw-r--r-- | arch/riscv/dts/hifive-unmatched-a00.dts | 3 | ||||
-rw-r--r-- | arch/riscv/include/asm/debug_ll.h | 14 |
9 files changed, 198 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index ea5ae0a6e9..c6875738d0 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -21,4 +21,23 @@ config SOC_VIRT Generates an image tht can be be booted by QEMU. The image is called barebox-dt-2nd.img +config SOC_SIFIVE + bool "SiFive SoCs" + select CLK_SIFIVE + select CLK_SIFIVE_PRCI + select RISCV_TIMER + select HAS_MACB + select HAS_ASM_DEBUG_LL + help + This enables support for SiFive SoC platform hardware. + +if SOC_SIFIVE + +config BOARD_HIFIVE + bool "HiFive" + depends on ARCH_RV64I + select USE_COMPRESSED_DTB + +endif + endmenu diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile index 2ce9af41e0..99f22f32b4 100644 --- a/arch/riscv/boards/Makefile +++ b/arch/riscv/boards/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/ +obj-$(CONFIG_BOARD_HIFIVE) += hifive/ diff --git a/arch/riscv/boards/hifive/Makefile b/arch/riscv/boards/hifive/Makefile new file mode 100644 index 0000000000..3d217ffe0b --- /dev/null +++ b/arch/riscv/boards/hifive/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.o diff --git a/arch/riscv/boards/hifive/lowlevel.c b/arch/riscv/boards/hifive/lowlevel.c new file mode 100644 index 0000000000..1de13cac16 --- /dev/null +++ b/arch/riscv/boards/hifive/lowlevel.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-riscv.h> +#include <debug_ll.h> + +ENTRY_FUNCTION(start_hifive_unmatched, a0, a1, a2) +{ + extern char __dtb_z_hifive_unmatched_a00_start[]; + + putc_ll('>'); + + barebox_riscv_entry(0x80000000, SZ_128M, + __dtb_z_hifive_unmatched_a00_start + get_runtime_offset()); +} + +ENTRY_FUNCTION(start_hifive_unleashed, a0, a1, a2) +{ + extern char __dtb_z_hifive_unleashed_a00_start[]; + + putc_ll('>'); + + barebox_riscv_entry(0x80000000, SZ_128M, + __dtb_z_hifive_unleashed_a00_start + get_runtime_offset()); +} diff --git a/arch/riscv/configs/sifive_defconfig b/arch/riscv/configs/sifive_defconfig new file mode 100644 index 0000000000..59cfebf194 --- /dev/null +++ b/arch/riscv/configs/sifive_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARCH_RV64I=y +CONFIG_SOC_SIFIVE=y +CONFIG_BOARD_HIFIVE=y +CONFIG_BOARD_RISCV_GENERIC_DT=y +CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_PANIC_HANG=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_IMD_TARGET=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_PARTITION_DISK_EFI=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_BAREBOXENV_TARGET=y +CONFIG_BAREBOXCRC32_TARGET=y +CONFIG_STATE=y +CONFIG_STATE_CRYPTO=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y +CONFIG_MACHINE_ID=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_POLLER=y +CONFIG_CMD_SLICE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_BOOTCHOOSER=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_CMP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_FBTEST=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_2048=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OF_FIXUP_STATUS=y +CONFIG_CMD_OF_OVERLAY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_FASTBOOT=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_DRIVER_SPI_GPIO=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_M25P80=y +CONFIG_DRIVER_CFI=y +CONFIG_DRIVER_CFI_BANK_WIDTH_8=y +CONFIG_DISK=y +CONFIG_DISK_WRITE=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIDEO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_EEPROM_AT24=y +CONFIG_HWRNG=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_GPIO_SIFIVE=y +# CONFIG_PINCTRL is not set +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_VIRTIO_MMIO=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UIMAGEFS=y +CONFIG_FS_PSTORE=y +CONFIG_FS_SQUASHFS=y +CONFIG_ZLIB=y +CONFIG_BZLIB=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DECOMPRESS=y +CONFIG_BASE64=y +CONFIG_DIGEST_CRC32_GENERIC=y diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 4041c34e0c..17fdc9445b 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -5,5 +5,7 @@ obj- += dummy.o pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o +pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \ + hifive-unleashed-a00.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..65694bfd24 --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 OR X11 */ + +#include <riscv/sifive/hifive-unleashed-a00.dts> diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts new file mode 100644 index 0000000000..b8793e9105 --- /dev/null +++ b/arch/riscv/dts/hifive-unmatched-a00.dts @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 OR X11 */ + +#include <riscv/sifive/hifive-unmatched-a00.dts> diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h index 598921910a..6904460af9 100644 --- a/arch/riscv/include/asm/debug_ll.h +++ b/arch/riscv/include/asm/debug_ll.h @@ -24,6 +24,20 @@ #include <asm/debug_ll_ns16550.h> +#elif defined CONFIG_DEBUG_SIFIVE + +#include <io.h> + +static inline void PUTC_LL(char ch) +{ + void __iomem *uart0 = IOMEM(0x10010000); + + while (readl(uart0) & 0x80000000) + ; + + writel(ch, uart0); +} + #endif #ifndef debug_ll_init |