Merge branch 'for-next/imx-usb-chipidea'

7 files changed, 45 insertions, 12 deletions

diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index 55087c2bc8..2a1278635e 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -231,8 +231,8 @@ static struct esdhc_platform_data sabrelite_sd4_data = {
 
 static void sabrelite_ehci_init(void)
 {
-	imx6_usb_phy1_disable_oc();
-	imx6_usb_phy1_enable();
+	imx6_usb_phy2_disable_oc();
+	imx6_usb_phy2_enable();
 
 	/* hub reset */
 	gpio_direction_output(204, 0);
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index f78d3d2bcd..f1b167aac5 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -205,6 +205,9 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);
 	clks[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,	"pll6_enet",	"osc", base + 0xe0, 0x3);
 
+	clks[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
+	clks[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+
 	clks[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
 	clks[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 	clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
@@ -298,6 +301,8 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clkdev_add_physbase(clks[ipg_per], MX6_I2C2_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg_per], MX6_I2C3_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ahb], MX6_SATA_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[usbphy1], MX6_USBPHY1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[usbphy2], MX6_USBPHY2_BASE_ADDR, NULL);
 
 	writel(0xffffffff, ccm_base + CCGR0);
 	writel(0xffffffff, ccm_base + CCGR1);
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 37ee5d8487..b62f4128cc 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -68,6 +68,7 @@ static int imx6_init(void)
 	add_generic_device("imx31-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
 	add_generic_device("imx31-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
 	add_generic_device("imx21-wdt", 0, NULL, MX6_WDOG1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx6-usb-misc", 0, NULL, MX6_USBOH3_USB_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL);
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h
index 0f17016530..a9c7e8dfeb 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx6.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx6.h
@@ -69,3 +69,29 @@ static inline struct device_d *imx6_add_sata(void)
 {
 	return add_generic_device("imx6-sata", 0, NULL, MX6_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
 }
+
+static inline struct device_d *imx6_add_usbotg(void *pdata)
+{
+	add_generic_device("imx-usb-phy", 0, NULL, MX6_USBPHY1_BASE_ADDR, 0x1000,
+			IORESOURCE_MEM, NULL);
+
+	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx6_add_usbh1(void *pdata)
+{
+	add_generic_device("imx-usb-phy", 1, NULL, MX6_USBPHY2_BASE_ADDR, 0x1000,
+			IORESOURCE_MEM, NULL);
+
+	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x200, 1, pdata);
+}
+
+static inline struct device_d *imx6_add_usbh2(void *pdata)
+{
+	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x400, 2, pdata);
+}
+
+static inline struct device_d *imx6_add_usbh3(void *pdata)
+{
+	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x600, 2, pdata);
+}
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 7c72cba838..d947aa6c9d 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -49,7 +49,8 @@
 #define MX6_WDOG2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x40000)
 #define MX6_CCM_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x44000)
 #define MX6_ANATOP_BASE_ADDR            (MX6_AIPS1_OFF_BASE_ADDR + 0x48000)
-#define MX6_USBPHY1_BASE_ADDR		(MX6_AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define MX6_USBPHY1_BASE_ADDR		(MX6_AIPS1_OFF_BASE_ADDR + 0x49000)
+#define MX6_USBPHY2_BASE_ADDR		(MX6_AIPS1_OFF_BASE_ADDR + 0x4a000)
 #define MX6_SNVS_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000)
 #define MX6_EPIT1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x50000)
 #define MX6_EPIT2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x54000)
diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h
index 0a88e7fe2c..85528d77e6 100644
--- a/arch/arm/mach-imx/include/mach/usb.h
+++ b/arch/arm/mach-imx/include/mach/usb.h
@@ -11,7 +11,7 @@
 #define MX35_H1_USBTE_BIT	(1 << 4)
 #define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
 
-int imx6_usb_phy1_disable_oc(void);
-int imx6_usb_phy1_enable(void);
+int imx6_usb_phy2_disable_oc(void);
+int imx6_usb_phy2_enable(void);
 
 #endif /* __MACH_USB_H_*/
diff --git a/arch/arm/mach-imx/usb-imx6.c b/arch/arm/mach-imx/usb-imx6.c
index cd234d2084..5e3df10e44 100644
--- a/arch/arm/mach-imx/usb-imx6.c
+++ b/arch/arm/mach-imx/usb-imx6.c
@@ -46,7 +46,7 @@
 #define USBPHY1_PLL_480_CTRL_EN_USB_CLK	(1 <<  6)
 #define USBPHY1_PLL_480_CTRL_BYPASS	(1 << 16)
 
-int imx6_usb_phy1_disable_oc(void)
+int imx6_usb_phy2_disable_oc(void)
 {
 	int val;
 
@@ -64,7 +64,7 @@ int imx6_usb_phy1_disable_oc(void)
 	return 0;
 }
 
-int imx6_usb_phy1_enable(void)
+int imx6_usb_phy2_enable(void)
 {
 	int val;
 
@@ -94,18 +94,18 @@ int imx6_usb_phy1_enable(void)
 	while (readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD) & USB_CMD_RESET);
 
 	/* reset usbphy */
-	writel(USBPHY_CTRL_SFTRST, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + SET);
+	writel(USBPHY_CTRL_SFTRST, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + SET);
 	udelay(10);
 	/* clr reset and clkgate */
-	writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + CLR);
+	writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + CLR);
 
 	/* clr all pwd bits => power up phy */
-	writel(0xffffffff, MX6_USBPHY1_BASE_ADDR + CLR);
+	writel(0xffffffff, MX6_USBPHY2_BASE_ADDR + CLR);
 
 	/* set utmilvl2/3 */
-	val = readl(MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL);
+	val = readl(MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL);
 	val |= USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2;
-	writel(val, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + SET);
+	writel(val, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + SET);
 
 	return 0;
 }