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author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-09-05 12:59:29 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-09-05 12:59:29 +0200 |
commit | b40aeb00d32f07c5b1b617ea4e88032cb895d8b3 (patch) | |
tree | f4161ad66628cd2c2733161d90c18bfa69eb5d8a /arch | |
parent | 6cb993c0cd0644d7b559cda6b84e4c196fc029dc (diff) | |
parent | 466b62f4f3ed361c0e60c8e345ffe2cb0733594e (diff) | |
download | barebox-b40aeb00d32f07c5b1b617ea4e88032cb895d8b3.tar.gz barebox-b40aeb00d32f07c5b1b617ea4e88032cb895d8b3.tar.xz |
Merge branch 'for-next/omap'
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boards/beagle/board.c | 9 | ||||
-rw-r--r-- | arch/arm/boards/panda/lowlevel.c | 4 | ||||
-rw-r--r-- | arch/arm/boards/panda/mux.c | 8 | ||||
-rw-r--r-- | arch/arm/boards/pcm049/board.c | 9 | ||||
-rw-r--r-- | arch/arm/boards/pcm049/lowlevel.c | 15 | ||||
-rw-r--r-- | arch/arm/boards/pcm049/mux.c | 8 | ||||
-rw-r--r-- | arch/arm/boards/phycard-a-l1/pca-a-l1.c | 9 | ||||
-rw-r--r-- | arch/arm/boards/phycard-a-xl2/lowlevel.c | 13 | ||||
-rw-r--r-- | arch/arm/boards/phycard-a-xl2/mux.c | 8 | ||||
-rw-r--r-- | arch/arm/boards/phycard-a-xl2/pca-a-xl2.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-omap/devices-gpmc-nand.c | 26 | ||||
-rw-r--r-- | arch/arm/mach-omap/gpmc.c | 61 | ||||
-rw-r--r-- | arch/arm/mach-omap/include/mach/gpmc.h | 16 | ||||
-rw-r--r-- | arch/arm/mach-omap/include/mach/gpmc_nand.h | 20 | ||||
-rw-r--r-- | arch/arm/mach-omap/include/mach/omap4-clock.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-omap/include/mach/omap4-silicon.h | 13 | ||||
-rw-r--r-- | arch/arm/mach-omap/omap4_clock.c | 58 | ||||
-rw-r--r-- | arch/arm/mach-omap/omap4_generic.c | 90 |
18 files changed, 309 insertions, 86 deletions
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c index 04a6611314..76c9be4fac 100644 --- a/arch/arm/boards/beagle/board.c +++ b/arch/arm/boards/beagle/board.c @@ -283,6 +283,12 @@ static struct i2c_board_info i2c_devices[] = { }, }; +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_HAMMING_CODE_HW_ROMCODE, + .nand_cfg = &omap3_nand_cfg, +}; + static int beagle_mem_init(void) { arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024); @@ -306,8 +312,7 @@ static int beagle_devices_init(void) /* WP is made high and WAIT1 active Low */ gpmc_generic_init(0x10); #endif - gpmc_generic_nand_devices_init(0, 16, - OMAP_ECC_HAMMING_CODE_HW_ROMCODE, &omap3_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K, IORESOURCE_MEM, NULL); diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c index 8591fff053..0b4b199d34 100644 --- a/arch/arm/boards/panda/lowlevel.c +++ b/arch/arm/boards/panda/lowlevel.c @@ -28,6 +28,8 @@ #include <mach/syslib.h> #include <asm/barebox-arm.h> +#define TPS62361_VSEL0_GPIO 7 + void set_muxconf_regs(void); static const struct ddr_regs ddr_regs_400_mhz_2cs = { @@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void) omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - omap4_scale_vcores(); + omap4_scale_vcores(TPS62361_VSEL0_GPIO); board_init_lowlevel_return(); } diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c index 310e43372f..3783006ad6 100644 --- a/arch/arm/boards/panda/mux.c +++ b/arch/arm/boards/panda/mux.c @@ -3,6 +3,7 @@ #include <io.h> #include <mach/omap4-silicon.h> #include <mach/omap4-mux.h> +#include <mach/omap4-clock.h> static const struct pad_conf_entry core_padconf_array[] = { { GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0 */ }, @@ -245,4 +246,11 @@ void set_muxconf_regs(void) omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_wk7 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio1_wup_clocks(); + } } diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c index 5b7854a5e3..3ef38a7831 100644 --- a/arch/arm/boards/pcm049/board.c +++ b/arch/arm/boards/pcm049/board.c @@ -94,6 +94,12 @@ static struct i2c_board_info i2c_devices[] = { }, }; +static struct gpmc_nand_platform_data nand_plat = { + .wait_mon_pin = 1, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap4_nand_cfg, +}; + static int pcm049_devices_init(void) { i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); @@ -107,8 +113,7 @@ static int pcm049_devices_init(void) pcm049_network_init(); - gpmc_generic_nand_devices_init(0, 8, - OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); #ifdef CONFIG_PARTITION devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw"); diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c index 5b9109833b..65a29ec8ae 100644 --- a/arch/arm/boards/pcm049/lowlevel.c +++ b/arch/arm/boards/pcm049/lowlevel.c @@ -28,6 +28,8 @@ #include <mach/syslib.h> #include <asm/barebox-arm.h> +#define TPS62361_VSEL0_GPIO 182 + void set_muxconf_regs(void); static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { @@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { static void noinline pcm049_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; @@ -57,12 +60,16 @@ static void noinline pcm049_init_lowlevel(void) omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - omap4_scale_vcores(); + omap4_scale_vcores(TPS62361_VSEL0_GPIO); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ - omap4_configure_mpu_dpll(&mpu); + if (omap4_revision() < OMAP4460_ES1_0) + omap4_configure_mpu_dpll(&mpu44xx); + else + omap4_configure_mpu_dpll(&mpu4460); + omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); @@ -88,7 +95,7 @@ void board_init_lowlevel(void) return; r = 0x4030d000; - __asm__ __volatile__("mov sp, %0" : : "r"(r)); + __asm__ __volatile__("mov sp, %0" : : "r"(r)); pcm049_init_lowlevel(); } diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c index a7a77b5adc..04e1d67214 100644 --- a/arch/arm/boards/pcm049/mux.c +++ b/arch/arm/boards/pcm049/mux.c @@ -3,6 +3,7 @@ #include <io.h> #include <mach/omap4-silicon.h> #include <mach/omap4-mux.h> +#include <mach/omap4-clock.h> static const struct pad_conf_entry core_padconf_array[] = { {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ @@ -242,4 +243,11 @@ void set_muxconf_regs(void) omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_182 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio_clocks(); + } } diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c index 00df240819..907198d783 100644 --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c +++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c @@ -391,9 +391,16 @@ struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = { }; #endif +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap3_nand_cfg, +}; + static int pcaal1_init_devices(void) { - gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_BCH8_CODE_HW, &omap3_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); + #ifdef CONFIG_MCI_OMAP_HSMMC add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K, IORESOURCE_MEM, &pcaal1_hsmmc_plat); diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c index b8de2aad0a..38f80c9733 100644 --- a/arch/arm/boards/phycard-a-xl2/lowlevel.c +++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c @@ -28,6 +28,8 @@ #include <mach/syslib.h> #include <asm/barebox-arm.h> +#define TPS62361_VSEL0_GPIO 7 + void set_muxconf_regs(void); static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { @@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { static noinline void pcaaxl2_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; @@ -57,12 +60,16 @@ static noinline void pcaaxl2_init_lowlevel(void) omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - omap4_scale_vcores(); + omap4_scale_vcores(TPS62361_VSEL0_GPIO); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ - omap4_configure_mpu_dpll(&mpu); + if (omap4_revision() < OMAP4460_ES1_0) + omap4_configure_mpu_dpll(&mpu44xx); + else + omap4_configure_mpu_dpll(&mpu4460); + omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); diff --git a/arch/arm/boards/phycard-a-xl2/mux.c b/arch/arm/boards/phycard-a-xl2/mux.c index 179e6b67ab..dc605e38b4 100644 --- a/arch/arm/boards/phycard-a-xl2/mux.c +++ b/arch/arm/boards/phycard-a-xl2/mux.c @@ -3,6 +3,7 @@ #include <io.h> #include <mach/omap4-silicon.h> #include <mach/omap4-mux.h> +#include <mach/omap4-clock.h> static const struct pad_conf_entry core_padconf_array[] = { {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ @@ -242,4 +243,11 @@ void set_muxconf_regs(void) omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_wk7 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio1_wup_clocks(); + } } diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c index 2132dc3c12..4fec0f0e41 100644 --- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c +++ b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c @@ -104,6 +104,12 @@ static struct omap_hsmmc_platform_data mmc_device = { #define OMAP4_MMC1_PBIASLITE_PWRDNZ (1<<22) #define OMAP4_MMC1_PWRDNZ (1<<26) +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap4_nand_cfg, +}; + static int pcaaxl2_devices_init(void) { u32 value; @@ -124,8 +130,7 @@ static int pcaaxl2_devices_init(void) pcaaxl2_network_init(); - gpmc_generic_nand_devices_init(0, 16, - OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); #ifdef CONFIG_PARTITION devfs_add_partition("nand0", 0x00000, SZ_128K, diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c index cf87b57d7f..64ca66619f 100644 --- a/arch/arm/mach-omap/devices-gpmc-nand.c +++ b/arch/arm/mach-omap/devices-gpmc-nand.c @@ -39,37 +39,23 @@ #define GPMC_CONF1_VALx8 0x00000800 #define GPMC_CONF1_VALx16 0x00001800 -/** NAND platform specific settings settings */ -static struct gpmc_nand_platform_data nand_plat = { - .cs = 0, - .max_timeout = MSECOND, - .wait_mon_pin = 0, -}; - /** * @brief gpmc_generic_nand_devices_init - init generic nand device * * @return success/fail based on device function */ -int gpmc_generic_nand_devices_init(int cs, int width, - enum gpmc_ecc_mode eccmode, struct gpmc_config *nand_cfg) +int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata) { - nand_plat.cs = cs; - - if (width == 16) - nand_cfg->cfg[0] = GPMC_CONF1_VALx16; + if (pdata->device_width == 16) + pdata->nand_cfg->cfg[0] = GPMC_CONF1_VALx16; else - nand_cfg->cfg[0] = GPMC_CONF1_VALx8; - - nand_plat.device_width = width; - nand_plat.ecc_mode = eccmode; - nand_plat.priv = nand_cfg; + pdata->nand_cfg->cfg[0] = GPMC_CONF1_VALx8; /* Configure GPMC CS before register */ - gpmc_cs_config(nand_plat.cs, nand_cfg); + gpmc_cs_config(pdata->cs, pdata->nand_cfg); add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, OMAP_GPMC_BASE, - 1024 * 4, IORESOURCE_MEM, &nand_plat); + 1024 * 4, IORESOURCE_MEM, pdata); return 0; } diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c index 92a8ae043d..5b4daaf031 100644 --- a/arch/arm/mach-omap/gpmc.c +++ b/arch/arm/mach-omap/gpmc.c @@ -31,6 +31,7 @@ #include <clock.h> #include <init.h> #include <io.h> +#include <errno.h> #include <mach/silicon.h> #include <mach/gpmc.h> #include <mach/sys_info.h> @@ -125,3 +126,63 @@ void gpmc_cs_config(char cs, struct gpmc_config *config) mdelay(1); /* Settling time */ } EXPORT_SYMBOL(gpmc_cs_config); + +#define CS_NUM_SHIFT 24 +#define ENABLE_PREFETCH (0x1 << 7) +#define DMA_MPU_MODE 2 + +/** + * gpmc_prefetch_enable - configures and starts prefetch transfer + * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write + * @dma_mode: dma mode enable (1) or disable (0) + * @u32_count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + */ +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write) +{ + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { + pr_err("gpmc: fifo threshold is not supported\n"); + return -EINVAL; + } + + /* Set the amount of bytes to be prefetched */ + writel(u32_count, GPMC_REG(PREFETCH_CONFIG2)); + + /* Set dma/mpu mode, the prefetch read / post write and + * enable the engine. Set which cs is has requested for. + */ + writel(((cs << CS_NUM_SHIFT) | PREFETCH_FIFOTHRESHOLD(fifo_th) | + ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | + (0x1 & is_write)), + GPMC_REG(PREFETCH_CONFIG1)); + + /* Start the prefetch engine */ + writel(0x1, GPMC_REG(PREFETCH_CONTROL)); + + return 0; +} +EXPORT_SYMBOL(gpmc_prefetch_enable); + +/** + * gpmc_prefetch_reset - disables and stops the prefetch engine + */ +int gpmc_prefetch_reset(int cs) +{ + u32 config1; + + /* check if the same module/cs is trying to reset */ + config1 = readl(GPMC_REG(PREFETCH_CONFIG1)); + if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) + return -EINVAL; + + /* Stop the PFPW engine */ + writel(0x0, GPMC_REG(PREFETCH_CONTROL)); + + /* Reset/disable the PFPW engine */ + writel(0x0, GPMC_REG(PREFETCH_CONFIG1)); + + return 0; +} +EXPORT_SYMBOL(gpmc_prefetch_reset); diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h index 3ddc5f5b87..ed4e82df7c 100644 --- a/arch/arm/mach-omap/include/mach/gpmc.h +++ b/arch/arm/mach-omap/include/mach/gpmc.h @@ -51,9 +51,10 @@ #define GPMC_TIMEOUT_CONTROL (0x40) #define GPMC_CFG (0x50) #define GPMC_STATUS (0x54) -#define GPMC_PREFETCH_CONFIG_1 (0x1E0) -#define GPMC_PREFETCH_CONFIG_2 (0x1E4) -#define GPMC_PREFETCH_CTRL (0x1EC) +#define GPMC_PREFETCH_CONFIG1 (0x1E0) +#define GPMC_PREFETCH_CONFIG2 (0x1E4) +#define GPMC_PREFETCH_CONTROL (0x1EC) +#define GPMC_PREFETCH_STATUS (0x1f0) #define GPMC_ECC_CONFIG (0x1F4) #define GPMC_ECC_CONTROL (0x1F8) #define GPMC_ECC_SIZE_CONFIG (0x1FC) @@ -138,6 +139,15 @@ #define GPMC_SIZE_32M 0x0E #define GPMC_SIZE_16M 0x0F +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) +#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) +#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) + +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write); +int gpmc_prefetch_reset(int cs); + #define NAND_WP_BIT 0x00000010 #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h index b9c659d1a9..582fb36e8f 100644 --- a/arch/arm/mach-omap/include/mach/gpmc_nand.h +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -50,10 +50,6 @@ struct gpmc_nand_platform_data { /** If there are any special setups you'd want to do */ int (*nand_setup) (struct gpmc_nand_platform_data *); - /** set up if we want H/w ECC here and other - * platform specific configs here - */ - unsigned short plat_options; /** ecc mode to use */ enum gpmc_ecc_mode ecc_mode; /** setup any special options */ @@ -62,24 +58,14 @@ struct gpmc_nand_platform_data { char device_width; /** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */ char wait_mon_pin; - /** Set this to the max timeout for the device */ - uint64_t max_timeout; /* if you like a custom oob use this. */ struct nand_ecclayout *oob; - /** platform specific private data */ - void *priv; + /** gpmc config for nand */ + struct gpmc_config *nand_cfg; }; -/** Platform specific options definitions */ -/** plat_options: Wait montioring pin low */ -#define NAND_WAITPOL_LOW (0 << 0) -/** plat_options: Wait montioring pin high */ -#define NAND_WAITPOL_HIGH (1 << 0) -#define NAND_WAITPOL_MASK (1 << 0) - -int gpmc_generic_nand_devices_init(int cs, int width, - enum gpmc_ecc_mode, struct gpmc_config *nand_cfg); +int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata); extern struct gpmc_config omap3_nand_cfg; extern struct gpmc_config omap4_nand_cfg; diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h index 0a31d09e06..e5302d6c74 100644 --- a/arch/arm/mach-omap/include/mach/omap4-clock.h +++ b/arch/arm/mach-omap/include/mach/omap4-clock.h @@ -271,6 +271,20 @@ #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 + /* Used to index into DPLL parameter tables */ struct dpll_param { unsigned int m; @@ -289,6 +303,8 @@ struct dpll_param { #define OMAP4_MPU_DPLL_PARAM_38M4 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} #define OMAP4_MPU_DPLL_PARAM_38M4_MPU600 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} #define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} +/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ +#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920 {0x23F, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} #define OMAP4_IVA_DPLL_PARAM_19M2 {0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00} #define OMAP4_IVA_DPLL_PARAM_38M4 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00} @@ -316,5 +332,8 @@ void omap4_configure_usb_dpll(const struct dpll_param *dpll_param); void omap4_configure_core_dpll_no_lock(const struct dpll_param *param); void omap4_lock_core_dpll(void); void omap4_lock_core_dpll_shadow(const struct dpll_param *param); +void omap4_enable_gpio1_wup_clocks(void); +void omap4_enable_gpio_clocks(void); void omap4_enable_all_clocks(void); +void omap4_do_scale_tps62361(u32 reg, u32 volt_mv); diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h index c7854751ad..4082bac34a 100644 --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h @@ -60,6 +60,13 @@ #define OMAP44XX_PRM_VC_VAL_BYPASS (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0) #define OMAP44XX_PRM_VC_CFG_I2C_MODE (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8) #define OMAP44XX_PRM_VC_CFG_I2C_CLK (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac) +#define OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_MASK 0xFF /* IRQ */ #define OMAP44XX_PRM_IRQSTATUS_MPU_A9 (OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010) @@ -94,6 +101,10 @@ #define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) #define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 #define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) + +/* Memory Adapter (4460 onwards) */ +#define OMAP44XX_MA_BASE 0x482AF000 + /* * Hardware Register Details */ @@ -178,6 +189,6 @@ struct dpll_param; void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *); void omap4_power_i2c_send(u32); unsigned int omap4_revision(void); -noinline int omap4_scale_vcores(void); +noinline int omap4_scale_vcores(unsigned vsel0_pin); #endif diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c index 3ab01f0d3a..1481f16ffd 100644 --- a/arch/arm/mach-omap/omap4_clock.c +++ b/arch/arm/mach-omap/omap4_clock.c @@ -1,6 +1,7 @@ #include <common.h> #include <io.h> #include <mach/syslib.h> +#include <mach/silicon.h> #include <mach/clocks.h> #define LDELAY 12000000 @@ -13,6 +14,10 @@ void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param) sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */ + /* Errata ID: i700, clear CM_CLKSEL_DPLL_MPU[22] : DCC_EN */ + if (omap4_revision() >= OMAP4460_ES1_0) + sr32(CM_CLKSEL_DPLL_MPU, 0, 22, 0); + /* Set M,N,M2 values */ sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param->m); sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param->n); @@ -197,6 +202,27 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param) wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY); } +void omap4_enable_gpio_clocks(void) +{ + sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); +} + +void omap4_enable_gpio1_wup_clocks(void) +{ + /* WKUP clocks */ + sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); +} + void omap4_enable_all_clocks(void) { /* Enable Ducati clocks */ @@ -254,16 +280,7 @@ void omap4_enable_all_clocks(void) wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); /* GPIO clocks */ - sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); + omap4_enable_gpio_clocks(); sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); @@ -313,8 +330,7 @@ void omap4_enable_all_clocks(void) wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART4_CLKCTRL, LDELAY); /* WKUP clocks */ - sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); + omap4_enable_gpio1_wup_clocks(); sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); @@ -378,3 +394,21 @@ void omap4_enable_all_clocks(void) sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); } +void omap4_do_scale_tps62361(u32 reg, u32 volt_mv) +{ + u32 temp, step; + + step = volt_mv - TPS62361_BASE_VOLT_MV; + step /= 10; + + temp = TPS62361_I2C_SLAVE_ADDR | + (reg << OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (step << OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT) | + OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT; + debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); + + writel(temp, OMAP44XX_PRM_VC_VAL_BYPASS); + if (!wait_on_value(OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT, 0, + OMAP44XX_PRM_VC_VAL_BYPASS, LDELAY)) + puts("Scaling voltage failed for vdd_mpu from TPS\n"); +} diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index de6993475d..617d786984 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -7,6 +7,7 @@ #include <mach/syslib.h> #include <mach/xload.h> #include <mach/gpmc.h> +#include <mach/gpio.h> /* * The following several lines are taken from U-Boot to support @@ -28,6 +29,10 @@ #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 + void __noreturn reset_cpu(unsigned long addr) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); @@ -263,14 +268,15 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs) static void reset_phy(unsigned int base) { - *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); + unsigned int val = readl(base + IODFT_TLGC); + val |= (1 << 10); + writel(val, base + IODFT_TLGC); } void omap4_ddr_init(const struct ddr_regs *ddr_regs, const struct dpll_param *core) { - unsigned int rev; - rev = omap4_revision(); + unsigned int rev = omap4_revision(); if (rev == OMAP4430_ES2_0) { writel(0x9e9e9e9e, 0x4A100638); @@ -290,8 +296,15 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* Both EMIFs 128 byte interleaved */ writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0); - *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; - *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; + writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2); + writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3); + + if (rev >= OMAP4460_ES1_0) { + writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0); + + writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2); + writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3); + } /* DDR needs to be initialised @ 19.2 MHz * So put core DPLL in bypass mode @@ -301,10 +314,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* No IDLE: BUG in SDC */ sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); + writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs); omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs); @@ -313,13 +326,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, omap4_lock_core_dpll_shadow(core); /* Set DLL_OVERRIDE = 0 */ - *(volatile int*)CM_DLL_CTRL = 0x0; + writel(0x0, CM_DLL_CTRL); delay(200); /* Check for DDR PHY ready for EMIF1 & EMIF2 */ - while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ - || (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); + while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \ + || ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04)); /* Reprogram the DDR PYHY Control register */ /* PHY control values */ @@ -331,9 +344,16 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* No IDLE: BUG in SDC */ //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + //while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); + writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); + + if (rev >= OMAP4460_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG); + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG); + } /* * DMM : DMM_LISA_MAP_0(Section_0) @@ -347,8 +367,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, reset_phy(OMAP44XX_EMIF1_BASE); reset_phy(OMAP44XX_EMIF2_BASE); - *((volatile int *)0x80000000) = 0; - *((volatile int *)0x80000080) = 0; + writel(0, 0x80000000); + writel(0, 0x80000080); } void omap4_power_i2c_send(u32 r) @@ -466,7 +486,7 @@ enum omap_boot_src omap4_bootsrc(void) #define I2C_SLAVE 0x12 -noinline int omap4_scale_vcores(void) +noinline int omap4_scale_vcores(unsigned vsel0_pin) { unsigned int rev = omap4_revision(); @@ -476,8 +496,41 @@ noinline int omap4_scale_vcores(void) writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE); writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK); + /* TPS - supplies vdd_mpu on 4460 */ + if (rev >= OMAP4460_ES1_0) { + /* + * Setup SET1 and SET0 with right values so that kernel + * can use either of them based on its needs. + */ + omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430); + omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430); + + /* + * Select SET1 in TPS62361: + * VSEL1 is grounded on board. So the following selects + * VSEL1 = 0 and VSEL0 = 1 + */ + gpio_direction_output(vsel0_pin, 0); + gpio_set_value(vsel0_pin, 1); + } + /* set VCORE1 force VSEL */ - omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE); + /* + * 4430 : supplies vdd_mpu + * Setting a high voltage for Nitro mode as smart reflex is not enabled. + * We use the maximum possible value in the AVS range because the next + * higher voltage in the discrete range (code >= 0b111010) is way too + * high + * + * 4460 : supplies vdd_core + * + */ + if (rev < OMAP4460_ES1_0) + /* 0x55: i2c addr, 3A: ~ 1430 mvolts*/ + omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE); + else + /* 0x55: i2c addr, 28: ~ 1200 mvolts*/ + omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE); /* FIXME: set VCORE2 force VSEL, Check the reset value */ omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE); @@ -490,6 +543,7 @@ noinline int omap4_scale_vcores(void) case OMAP4430_ES2_1: omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE); break; + /* > OMAP4460_ES1_0 : VCORE3 not connected */ } return 0; |