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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2012-07-06 14:34:28 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-07-09 09:23:35 +0200 |
| commit | bdf8405e34df9eeb75cb71801363509a7ab91536 (patch) | |
| tree | 71f75c810fac11c8eb350f628993cdd41732f37d /arch | |
| parent | b35fb39d32714798aa0f14e44ec794bc7d5cd366 (diff) | |
| download | barebox-bdf8405e34df9eeb75cb71801363509a7ab91536.tar.gz barebox-bdf8405e34df9eeb75cb71801363509a7ab91536.tar.xz | |
MIPS: remove unused processor-specific constants and macros
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/asm.h | 8 | ||||
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 32 |
2 files changed, 0 insertions, 40 deletions
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 608cfcfbb3..12e17581b8 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -398,12 +398,4 @@ symbol = value #define SSNOP sll zero, zero, 1 -#ifdef CONFIG_SGI_IP28 -/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ -#include <asm/cacheops.h> -#define R10KCBARRIER(addr) cache Cache_Barrier, addr; -#else -#define R10KCBARRIER(addr) -#endif - #endif /* __ASM_ASM_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index befccbb95e..16ba38e50d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -102,11 +102,6 @@ #define CP0_S3_SRSMAP $12 /* MIPSR2 */ /* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* * Coprocessor 1 (FPU) register names */ #define CP1_REVISION $0 @@ -387,27 +382,6 @@ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - /* Bits specific to the R30xx. */ #define R30XX_CONF_FDM (_ULCAST_(1) << 19) #define R30XX_CONF_REV (_ULCAST_(1) << 22) @@ -419,12 +393,6 @@ #define R30XX_CONF_SB (_ULCAST_(1) << 30) #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - /* Bits specific to the MIPS32/64 PRA. */ #define MIPS_CONF_MT (_ULCAST_(7) << 7) #define MIPS_CONF_AR (_ULCAST_(7) << 10) |