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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-02-26 19:16:55 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-03-04 08:43:55 +0100 |
| commit | c668288edc8d2c6d5362d16be0aff797ac514eab (patch) | |
| tree | 7ea3a93a3348821fa475762407ec4ccea360946e /arch | |
| parent | e986cb4503a2ccc0c70232ecd693650634d8b6a5 (diff) | |
| download | barebox-c668288edc8d2c6d5362d16be0aff797ac514eab.tar.gz barebox-c668288edc8d2c6d5362d16be0aff797ac514eab.tar.xz | |
ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2
Enable PCIE1 and PCIE2 used on both Zest and RMB3 boards.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx8mq-zii-ultra.dtsi | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi index a6b2b89662..c618f04565 100644 --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi @@ -37,6 +37,18 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; }; &fec1 { @@ -227,6 +239,41 @@ barebox,provide-mac-address = <&fec1 0x640>; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; + + host@0 { + reg = <0 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + i210: i210@0 { + reg = <0 0 0 0 0>; + }; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -344,6 +391,20 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x76 + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x76 + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16 + >; + }; + pinctrl_reg_usdhc2: regusdhc2grpgpio { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |