diff options
| author | Fabian Godehardt <fg@emlix.com> | 2018-12-05 16:40:36 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-06 09:07:02 +0100 |
| commit | ca343ec8a2d09ab0708cb007ac0382960a31b218 (patch) | |
| tree | a0581fa9e17a0996b7fffc09291fdda7f9591dfc /arch | |
| parent | 6304b2bcc84380ebbceaa95525d915106635b789 (diff) | |
| download | barebox-ca343ec8a2d09ab0708cb007ac0382960a31b218.tar.gz barebox-ca343ec8a2d09ab0708cb007ac0382960a31b218.tar.xz | |
ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1
Enable USB OTG support on USB OTG port 1 of the phyCORE-i.MX 6UL/ULL.
Signed-off-by: Fabian Godehardt <fg@emlix.com>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx6ul-phytec-phycore-som.dts | 4 | ||||
| -rw-r--r-- | arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 14 | ||||
| -rw-r--r-- | arch/arm/dts/imx6ull-phytec-phycore-som.dts | 4 |
3 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts index 5094243470..6d1876702d 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -40,6 +40,10 @@ status = "okay"; }; +&usbotg1 { + status = "okay"; +}; + &usbotg2 { status = "okay"; }; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index 05bf18d6f1..d829fdd6fb 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -89,6 +89,14 @@ status = "disabled"; }; +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + disable-over-current; + status = "disabled"; +}; + &usbotg2 { dr_mode = "host"; disable-over-current; @@ -169,6 +177,12 @@ >; }; + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts index de04132a02..ce631460ca 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts @@ -39,3 +39,7 @@ &usdhc1 { status = "okay"; }; + +&usbotg1 { + status = "okay"; +}; |