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authorChristian Hemp <c.hemp@phytec.de>2015-11-09 10:02:51 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-11-11 08:39:41 +0100
commite4c00a8b11b84bd4cf3bc643a58ac26b5dde3347 (patch)
treec82a1a92f308314e8f1be19148dab857f0562bd5 /arch
parent813d5e00bf1e05018341612214db185ce0b65a95 (diff)
downloadbarebox-e4c00a8b11b84bd4cf3bc643a58ac26b5dde3347.tar.gz
barebox-e4c00a8b11b84bd4cf3bc643a58ac26b5dde3347.tar.xz
ARM: imx6dl: Add support for Phytec phyCORE-i.MX6 SOM
Add Phytec phyCORE-i.MX6 SOM. - imx6dl-phytec-phycore-som-nand - 256GB RAM on 1 Bank with 32Bit - 10/100MBit Ethernet - NAND - SD - UART Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boards/phytec-som-imx6/board.c6
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg8
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h98
-rw-r--r--arch/arm/boards/phytec-som-imx6/lowlevel.c1
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts63
6 files changed, 176 insertions, 3 deletions
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index 639a562525..9aefa552c3 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -112,7 +112,8 @@ static int physom_imx6_devices_init(void)
default_envdev = "NAND flash";
} else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
- || of_machine_is_compatible("phytec,imx6q-pcm058-emmc")) {
+ || of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
+ || of_machine_is_compatible("phytec,imx6dl-pcm058-nand")) {
barebox_set_hostname("phyCORE-i.MX6");
default_environment_path = "/chosen/environment-spinor";
@@ -157,7 +158,8 @@ static int physom_imx6_devices_init(void)
/* Overwrite file /env/init/automount */
if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
- || of_machine_is_compatible("phytec,imx6q-pcm058-emmc")) {
+ || of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
+ || of_machine_is_compatible("phytec,imx6dl-pcm058-nand")) {
defaultenv_append_directory(defaultenv_physom_imx6_mira);
}
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg
new file mode 100644
index 0000000000..bf50190c78
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg
@@ -0,0 +1,8 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x3c409b85
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021b0040 0x0000000F; \
+ wm 32 0x021b0000 0x82190000
+
+#include "flash-header-phytec-pcm058dl.h"
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h
new file mode 100644
index 0000000000..c7df7907d1
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h
@@ -0,0 +1,98 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+wm 32 0x020e0774 0x000C0000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0494 0x00000030
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00000030
+wm 32 0x020e04b8 0x00000030
+wm 32 0x020e04a4 0x00003000
+wm 32 0x020e04a8 0x00003000
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e04bc 0x00000028
+wm 32 0x020e04c0 0x00000028
+wm 32 0x020e04c4 0x00000028
+wm 32 0x020e04c8 0x00000028
+wm 32 0x020e04cc 0x00000028
+wm 32 0x020e04d0 0x00000028
+wm 32 0x020e04d4 0x00000028
+wm 32 0x020e04d8 0x00000028
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0764 0x00000028
+wm 32 0x020e0770 0x00000028
+wm 32 0x020e0778 0x00000028
+wm 32 0x020e077c 0x00000028
+wm 32 0x020e0780 0x00000028
+wm 32 0x020e0784 0x00000028
+wm 32 0x020e078c 0x00000028
+wm 32 0x020e0748 0x00000028
+wm 32 0x020e0470 0x00000028
+wm 32 0x020e0474 0x00000028
+wm 32 0x020e0478 0x00000028
+wm 32 0x020e047c 0x00000028
+wm 32 0x020e0480 0x00000028
+wm 32 0x020e0484 0x00000028
+wm 32 0x020e0488 0x00000028
+wm 32 0x020e048c 0x00000028
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b080c 0x0032003A
+wm 32 0x021b0810 0x00350037
+wm 32 0x021b480c 0x00260038
+wm 32 0x021b4810 0x002C0038
+wm 32 0x021b083c 0x42630244
+wm 32 0x021b0840 0x02300238
+wm 32 0x021b483c 0x02540258
+wm 32 0x021b4840 0x0236021e
+wm 32 0x021b0848 0x46484446
+wm 32 0x021b4848 0x302d2c35
+wm 32 0x021b0850 0x36342630
+wm 32 0x021b4850 0x3423372d
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0008 0x09444040
+
+SETUP_MDCFG0
+
+wm 32 0x021b0010 0xff538f64
+wm 32 0x021b0014 0x01ff0124
+wm 32 0x021b0018 0x00091740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x003F1023
+
+SETUP_MDASP_MDCTL
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0020 0x00007800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 555487b0c5..eb796e78b8 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -92,5 +92,6 @@ PHYTEC_ENTRY(start_phytec_pbab01s_512mb_1bank, imx6s_phytec_pbab01, SZ_512M, fal
PHYTEC_ENTRY(start_phytec_phyboard_alcor_1gib, imx6q_phytec_phyboard_alcor, SZ_1G, false);
PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_subra, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e239c5e8f..f5bf033583 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -45,7 +45,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
imx6q-phytec-phyboard-alcor.dtb.o \
imx6dl-phytec-phyboard-subra.dtb.o \
imx6q-phytec-phycore-som-nand.dtb.o \
- imx6q-phytec-phycore-som-emmc.dtb.o
+ imx6q-phytec-phycore-som-emmc.dtb.o \
+ imx6dl-phytec-phycore-som-nand.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
new file mode 100644
index 0000000000..2324f3a6e5
--- /dev/null
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <arm/imx6dl.dtsi>
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+/ {
+ model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND";
+ compatible = "phytec,imx6dl-pcm058-nand", "fsl,imx6dl";
+};
+
+&eeprom {
+ status = "okay";
+};
+
+&fec {
+ status = "okay";
+ phy-handle = <&ethphy>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 14 1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@3 {
+ reg = <3>;
+ max-speed = <100>;
+ };
+ };
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@1 {
+ label = "barebox-environment";
+ reg = <0x80000 0x80000>;
+ };
+};