ARM: socfpga: sockit: update handoff files to 14.0

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

8 files changed, 396 insertions, 138 deletions

diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
index 96045d50d6..117d7f4ebc 100644
--- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
@@ -1,4 +1,31 @@
-/* This file is generated by Preloader Generator */
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include <mach/scan-manager.h>
 
@@ -121,7 +148,7 @@ static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2
 
 static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
 	0x0C420D80,
-	0x882000FF,
+	0x082000FF,
 	0x0A804001,
 	0x07900000,
 	0x08020000,
diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c
index 554fbd8fef..3a7cd2bc62 100644
--- a/arch/arm/boards/terasic-sockit/pinmux_config.c
+++ b/arch/arm/boards/terasic-sockit/pinmux_config.c
@@ -1,3 +1,32 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
 #include <common.h>
 
 unsigned long sys_mgr_init_table[] = {
diff --git a/arch/arm/boards/terasic-sockit/pll_config.h b/arch/arm/boards/terasic-sockit/pll_config.h
index 672ce41fb7..e064e2b2b2 100644
--- a/arch/arm/boards/terasic-sockit/pll_config.h
+++ b/arch/arm/boards/terasic-sockit/pll_config.h
@@ -1,98 +1,113 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _PRELOADER_PLL_CONFIG_H_
 #define _PRELOADER_PLL_CONFIG_H_
 
-/* PLL configuration data */
-/* Main PLL */
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM			(0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(63)
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(15)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK		(1)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK		(0)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK		(1)
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK		(0)
-/*
- * To tell where is the clock source:
- * 0 = MAINPLL
- * 1 = PERIPHPLL
- */
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP		(1)
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP		(1)
+#define CONFIG_HPS_DBCTRL_STAYOSC1 (1)
 
-/* Peripheral PLL */
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM			(1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER			(79)
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC			(0)
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT		(3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		(3)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		(1)
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT	(19)
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT		(4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		(9)
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK			(0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		(0)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK		(1)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK		(1)
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK		(6249)
-/*
- * To tell where is the clock source:
- * 0 = F2S_PERIPH_REF_CLK
- * 1 = MAIN_CLK
- * 2 = PERIPH_CLK
- */
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC			(2)
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND			(2)
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI			(1)
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
 
-/* SDRAM PLL */
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(0)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(31)
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC			(0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT		(1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE		(0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT		(0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE		(0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT		(1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE		(4)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT		(5)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE		(0)
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ (12500000)
+#define CONFIG_HPS_CLK_CAN1_HZ (12500000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
 
-/* Info for driver */
-#define CONFIG_HPS_CLK_OSC1_HZ			(25000000)
-#define CONFIG_HPS_CLK_MAINVCO_HZ		(1600000000)
-#define CONFIG_HPS_CLK_PERVCO_HZ		(1000000000)
-#define CONFIG_HPS_CLK_SDRVCO_HZ		(600000000)
-#define CONFIG_HPS_CLK_EMAC0_HZ			(50000000)
-#define CONFIG_HPS_CLK_EMAC1_HZ			(50000000)
-#define CONFIG_HPS_CLK_USBCLK_HZ		(200000000)
-#define CONFIG_HPS_CLK_NAND_HZ			(100000000)
-#define CONFIG_HPS_CLK_SDMMC_HZ			(50000000)
-#define CONFIG_HPS_CLK_QSPI_HZ			(400000000)
-#define CONFIG_HPS_CLK_SPIM_HZ			(200000000)
-#define CONFIG_HPS_CLK_CAN0_HZ			(100000000)
-#define CONFIG_HPS_CLK_CAN1_HZ			(100000000)
-#define CONFIG_HPS_CLK_GPIODB_HZ		(32000)
-#define CONFIG_HPS_CLK_L4_MP_HZ			(100000000)
-#define CONFIG_HPS_CLK_L4_SP_HZ			(100000000)
+#define CONFIG_HPS_ALTERAGRP_MPUCLK (1)
+#define CONFIG_HPS_ALTERAGRP_MAINCLK (3)
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3)
 
 #endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/arch/arm/boards/terasic-sockit/sdram_config.h b/arch/arm/boards/terasic-sockit/sdram_config.h
index 2c04b02599..875d5fe0e7 100644
--- a/arch/arm/boards/terasic-sockit/sdram_config.h
+++ b/arch/arm/boards/terasic-sockit/sdram_config.h
@@ -1,3 +1,32 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
 #ifndef __SDRAM_CONFIG_H
 #define __SDRAM_CONFIG_H
 
@@ -26,9 +55,10 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			(20)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			(4)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			(4)
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		(200)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		(512)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		(3)
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	(0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	(8)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		(10)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		(15)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		(3)
@@ -36,6 +66,7 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		(32)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		(8)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		(3)
 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			(2)
 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		(0)
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		(2)
@@ -61,9 +92,12 @@
 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	(0)
 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	(0x41041041)
 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	(0x410410)
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x01010101)
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x01010101)
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x0101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
+(0x0101)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			(0)
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			(1)
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED	(0x0)
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto.h b/arch/arm/boards/terasic-sockit/sequencer_auto.h
index 492706f7a3..ac6d28297d 100644
--- a/arch/arm/boards/terasic-sockit/sequencer_auto.h
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto.h
@@ -1,3 +1,31 @@
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
 #define __RW_MGR_ac_mrs1 0x04
 #define __RW_MGR_ac_mrs3 0x06
 #define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
@@ -71,56 +99,83 @@
 #define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
 #define __RW_MGR_CONTENT_ac_mrs2 0x100A0218
 
-#define __RW_MGR_READ_B2B_WAIT2 0x6A
-#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#define __RW_MGR_READ_B2B_WAIT2 0x6B
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
 #define __RW_MGR_REFRESH_ALL 0x14
 #define __RW_MGR_ZQCL 0x06
-#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
-#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
+#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
 #define __RW_MGR_ACTIVATE_0_AND_1 0x0D
 #define __RW_MGR_MRS2_MIRR 0x0A
-#define __RW_MGR_INIT_RESET_0_CKE_0 0x6E
-#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
+#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
 #define __RW_MGR_ACTIVATE_1 0x0F
 #define __RW_MGR_MRS2 0x04
-#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
 #define __RW_MGR_MRS1 0x03
-#define __RW_MGR_IDLE_LOOP1 0x7C
-#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
+#define __RW_MGR_IDLE_LOOP1 0x7B
+#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
 #define __RW_MGR_MRS3 0x05
-#define __RW_MGR_IDLE_LOOP2 0x7B
-#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
-#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
-#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#define __RW_MGR_RDIMM_CMD 0x7A
-#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
-#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
-#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
-#define __RW_MGR_GUARANTEED_READ_CONT 0x53
+#define __RW_MGR_IDLE_LOOP2 0x7A
+#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define __RW_MGR_RDIMM_CMD 0x79
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define __RW_MGR_GUARANTEED_READ_CONT 0x54
+#define __RW_MGR_REFRESH_DELAY 0x15
 #define __RW_MGR_MRS3_MIRR 0x0B
 #define __RW_MGR_IDLE 0x00
-#define __RW_MGR_READ_B2B 0x58
-#define __RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
-#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
-#define __RW_MGR_GUARANTEED_WRITE 0x17
+#define __RW_MGR_READ_B2B 0x59
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define __RW_MGR_GUARANTEED_WRITE 0x18
 #define __RW_MGR_PRECHARGE_ALL 0x12
-#define __RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
-#define __RW_MGR_SGLE_READ 0x7E
+#define __RW_MGR_SGLE_READ 0x7D
 #define __RW_MGR_MRS0_USER_MIRR 0x0C
 #define __RW_MGR_RETURN 0x01
-#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
 #define __RW_MGR_MRS0_USER 0x07
-#define __RW_MGR_GUARANTEED_READ 0x4B
+#define __RW_MGR_GUARANTEED_READ 0x4C
 #define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define __RW_MGR_INIT_RESET_1_CKE_0 0x73
+#define __RW_MGR_INIT_RESET_1_CKE_0 0x74
 #define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
 #define __RW_MGR_MRS0_DLL_RESET 0x02
 #define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define __RW_MGR_LFSR_WR_RD_BANK_0 0x21
-#define __RW_MGR_CLEAR_DQS_ENABLE 0x48
+#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define __RW_MGR_CLEAR_DQS_ENABLE 0x49
 #define __RW_MGR_MRS1_MIRR 0x09
-#define __RW_MGR_READ_B2B_WAIT1 0x60
+#define __RW_MGR_READ_B2B_WAIT1 0x61
 #define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
 #define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
 #define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
@@ -147,14 +202,13 @@
 #define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
 #define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
 #define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
+#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680
 #define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
 #define __RW_MGR_CONTENT_IDLE 0x080000
 #define __RW_MGR_CONTENT_READ_B2B 0x040E88
-#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
 #define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
 #define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
 #define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
-#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
 #define __RW_MGR_CONTENT_SGLE_READ 0x040F08
 #define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
 #define __RW_MGR_CONTENT_RETURN 0x080680
@@ -171,3 +225,4 @@
 #define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
 #define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
 #define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
+
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
index 5b0c3f351d..fe0764b0ce 100644
--- a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
@@ -1,3 +1,32 @@
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
 static const uint32_t ac_rom_init_size = 36;
 static const uint32_t ac_rom_init[36] =
 {
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
index 7815faa939..fc83721ea2 100644
--- a/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
@@ -1,7 +1,35 @@
-#include <common.h>
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
 
-const uint32_t inst_rom_init_size = 128;
-const uint32_t inst_rom_init[128] =
+#include <common.h>
+const uint32_t inst_rom_init_size = 127;
+const uint32_t inst_rom_init[127] =
 {
 	0x80000,
 	0x80680,
@@ -24,6 +52,7 @@ const uint32_t inst_rom_init[128] =
 	0x900,
 	0x80680,
 	0x980,
+	0xa680,
 	0x8680,
 	0x80680,
 	0xb68,
@@ -114,16 +143,14 @@ const uint32_t inst_rom_init[128] =
 	0xe680,
 	0x80680,
 	0x0,
-	0x0,
-	0xa000,
 	0x8000,
+	0xa000,
+	0xc000,
 	0x80000,
 	0x80,
-	0x80,
-	0x80,
-	0x80,
-	0xa080,
 	0x8080,
+	0xa080,
+	0xc080,
 	0x80080,
 	0x9180,
 	0x8680,
diff --git a/arch/arm/boards/terasic-sockit/sequencer_defines.h b/arch/arm/boards/terasic-sockit/sequencer_defines.h
index a3cd7a87d7..f4d43951c8 100644
--- a/arch/arm/boards/terasic-sockit/sequencer_defines.h
+++ b/arch/arm/boards/terasic-sockit/sequencer_defines.h
@@ -1,3 +1,31 @@
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
 #ifndef _SEQUENCER_DEFINES_H_
 #define _SEQUENCER_DEFINES_H_
 
@@ -30,6 +58,7 @@
 #define DM_PINS_ENABLED 1
 #define ENABLE_ASSERT 0
 #define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DELAY_CHAIN_WRITE 0
 #define ENABLE_DQS_IN_CENTERING 1
 #define ENABLE_DQS_OUT_CENTERING 0
 #define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
@@ -38,6 +67,7 @@
 #define ENABLE_NON_DESTRUCTIVE_CALIB 0
 #define ENABLE_SUPER_QUICK_CALIBRATION 0
 #define ENABLE_TCL_DEBUG 0
+#define FAKE_CAL_FAIL 0
 #define FULL_RATE 1
 #define GUARANTEED_READ_BRINGUP_TEST 0
 #define HALF_RATE 0
@@ -69,9 +99,13 @@
 #define LPDDR1 0
 #define LPDDR2 0
 #define LRDIMM 0
+#define M10_DQ_WIDTH_8 0
+#define M10_DQ_WIDTH_16 0
+#define M10_DQ_WIDTH_24 0
 #define MARGIN_VARIATION_TEST 0
 #define MAX_LATENCY_COUNT_WIDTH 5
 #define MEM_ADDR_WIDTH 13
+#define MRS_MIRROR_PING_PONG_ATSO 0
 #define MULTIPLE_AFI_WLAT 0
 #define NUM_SHADOW_REGS 1
 #define QDRII 0
@@ -79,7 +113,7 @@
 #define RDIMM 0
 #define READ_AFTER_WRITE_CALIBRATION 1
 #define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
 #define RLDRAM3 0
 #define RLDRAMII 0
 #define RLDRAMX 0
@@ -110,9 +144,17 @@
 #define STATIC_SIM_FILESET 0
 #define STATIC_SKIP_MEM_INIT 0
 #define STRATIXV 0
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TINIT_CNTR0_VAL 99
 #define TRACKING_ERROR_TEST 0
 #define TRACKING_WATCH_TEST 0
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+#define TRESET_CNTR0_VAL 99
+#define TW0_CAPTURE_CLOCKS 0
 #define USE_DQS_TRACKING 1
 #define USE_SHADOW_REGS 0
+#define USE_USER_RDIMM_VALUE 0
 
 #endif /* _SEQUENCER_DEFINES_H_ */