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author | Sascha Hauer <s.hauer@pengutronix.de> | 2011-12-16 15:15:30 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-01-02 15:00:28 +0100 |
commit | e9cff5cb4a0994680cc5831b8b483860a5feb15d (patch) | |
tree | d910937f7abf35ec536a465bc9074fceb84cb04a /arch | |
parent | 1679cebce784def9f2e1423b22bda4d36aa631dc (diff) | |
download | barebox-e9cff5cb4a0994680cc5831b8b483860a5feb15d.tar.gz barebox-e9cff5cb4a0994680cc5831b8b483860a5feb15d.tar.xz |
ARM i.MX51: implement a imx51_lowlevel_init
Reimplement the code from lowlevel.S in C. It is run
from SDRAM anyway, so we can safely do this initialization
in a regular barebox environment instead in Assembly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-imx/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-imx/imx51.c | 105 | ||||
-rw-r--r-- | arch/arm/mach-imx/include/mach/imx5.h | 1 |
3 files changed, 107 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 38de346eca..a9aa9e2655 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o -obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o +obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o obj-$(CONFIG_IMX_CLKO) += clko.o obj-$(CONFIG_IMX_IIM) += iim.o diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index 2c1efed150..2431e61115 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -21,6 +21,8 @@ #include <environment.h> #include <io.h> #include <mach/imx51-regs.h> +#include <mach/imx5.h> +#include <mach/clock-imx51_53.h> #include "gpio.h" @@ -176,3 +178,106 @@ static int imx51_boot_save_loc(void) } coredevice_initcall(imx51_boot_save_loc); + +#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5) +#define setup_pll_800(base) imx5_setup_pll((base), 800, ((8 << 4) + ((1 - 1) << 0)), (3 - 1), 1) +#define setup_pll_665(base) imx5_setup_pll((base), 665, ((6 << 4) + ((1 - 1) << 0)), (96 - 1), 89) +#define setup_pll_400(base) imx5_setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1) +#define setup_pll_455(base) imx5_setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23) +#define setup_pll_216(base) imx5_setup_pll((base), 216, ((6 << 4) + ((3 - 1) << 0)), (4 - 1), 3) + +void imx51_init_lowlevel(void) +{ + void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR; + u32 r; + + imx5_init_lowlevel(); + + /* disable write combine for TO 2 and lower revs */ + if (imx_silicon_revision() < MX51_CHIP_REV_3_0) { + __asm__ __volatile__("mrc 15, 1, %0, c9, c0, 1":"=r"(r)); + r |= (1 << 25); + __asm__ __volatile__("mcr 15, 1, %0, c9, c0, 1" : : "r"(r)); + } + + /* Gate of clocks to the peripherals first */ + writel(0x3fffffff, ccm + MX5_CCM_CCGR0); + writel(0x00000000, ccm + MX5_CCM_CCGR1); + writel(0x00000000, ccm + MX5_CCM_CCGR2); + writel(0x00000000, ccm + MX5_CCM_CCGR3); + writel(0x00030000, ccm + MX5_CCM_CCGR4); + writel(0x00fff030, ccm + MX5_CCM_CCGR5); + writel(0x00000300, ccm + MX5_CCM_CCGR6); + + /* Disable IPU and HSC dividers */ + writel(0x00060000, ccm + MX5_CCM_CCDR); + + /* Make sure to switch the DDR away from PLL 1 */ + writel(0x19239145, ccm + MX5_CCM_CBCDR); + /* make sure divider effective */ + while (readl(ccm + MX5_CCM_CDHIPR)); + + /* Switch ARM to step clock */ + writel(0x4, ccm + MX5_CCM_CCSR); + + setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR); + setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR); + + /* Switch peripheral to PLL 3 */ + writel(0x000010C0, ccm + MX5_CCM_CBCMR); + writel(0x13239145, ccm + MX5_CCM_CBCDR); + + setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR); + + /* Switch peripheral to PLL2 */ + writel(0x19239145, ccm + MX5_CCM_CBCDR); + writel(0x000020C0, ccm + MX5_CCM_CBCMR); + + setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR); + + /* Set the platform clock dividers */ + writel(0x00000124, MX51_ARM_BASE_ADDR + 0x14); + + /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */ + if (imx_silicon_revision() == MX51_CHIP_REV_3_0) + writel(0x0, ccm + MX5_CCM_CACRR); + else + writel(0x1, ccm + MX5_CCM_CACRR); + + /* Switch ARM back to PLL 1 */ + writel(0x0, ccm + MX5_CCM_CCSR); + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + writel(0x000020C2, ccm + MX5_CCM_CBCMR); + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ + writel(0x59239100, ccm + MX5_CCM_CBCDR); + + /* Restore the default values in the Gate registers */ + writel(0xffffffff, ccm + MX5_CCM_CCGR0); + writel(0xffffffff, ccm + MX5_CCM_CCGR1); + writel(0xffffffff, ccm + MX5_CCM_CCGR2); + writel(0xffffffff, ccm + MX5_CCM_CCGR3); + writel(0xffffffff, ccm + MX5_CCM_CCGR4); + writel(0xffffffff, ccm + MX5_CCM_CCGR5); + writel(0xffffffff, ccm + MX5_CCM_CCGR6); + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + writel(0xA5A2A020, ccm + MX5_CCM_CSCMR1); + writel(0x00C30321, ccm + MX5_CCM_CSCDR1); + + /* make sure divider effective */ + while (readl(ccm + MX5_CCM_CDHIPR)); + + writel(0x0, ccm + MX5_CCM_CCDR); + + writel(0x1, 0x73fa8074); + + r = readl(0x73f88000); + r |= 0x40; + writel(r, 0x73f88000); + + r = readl(0x73f88004); + r |= 0x40; + writel(r, 0x73f88004); +} diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h index d0340827c5..04911797a3 100644 --- a/arch/arm/mach-imx/include/mach/imx5.h +++ b/arch/arm/mach-imx/include/mach/imx5.h @@ -2,6 +2,7 @@ #define __MACH_MX5_H void imx53_init_lowlevel(void); +void imx51_init_lowlevel(void); void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn); void imx5_init_lowlevel(void); |