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| author | Jan Weitzel <j.weitzel@phytec.de> | 2012-08-02 12:55:59 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-08-13 20:41:22 +0200 |
| commit | ed3588344251661f7b5a5649fd1feb661656913e (patch) | |
| tree | 4ccd7a03357b27f8524e0a7ab1a2a6de684fd957 /arch | |
| parent | cf63079a2b73f8e2bb63bf87babb89b741b774c1 (diff) | |
| download | barebox-ed3588344251661f7b5a5649fd1feb661656913e.tar.gz barebox-ed3588344251661f7b5a5649fd1feb661656913e.tar.xz | |
ARM OMAP4: use writel and readl
replace *(volatile int*) by writel and readl
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap/omap4_generic.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index de6993475d..28fb776f84 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -263,7 +263,9 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs) static void reset_phy(unsigned int base) { - *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); + unsigned int val = readl(base + IODFT_TLGC); + val |= (1 << 10); + writel(val, base + IODFT_TLGC); } void omap4_ddr_init(const struct ddr_regs *ddr_regs, @@ -290,8 +292,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* Both EMIFs 128 byte interleaved */ writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0); - *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; - *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; + writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2); + writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3); /* DDR needs to be initialised @ 19.2 MHz * So put core DPLL in bypass mode @@ -301,10 +303,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* No IDLE: BUG in SDC */ sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); + writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs); omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs); @@ -313,13 +315,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, omap4_lock_core_dpll_shadow(core); /* Set DLL_OVERRIDE = 0 */ - *(volatile int*)CM_DLL_CTRL = 0x0; + writel(0x0, CM_DLL_CTRL); delay(200); /* Check for DDR PHY ready for EMIF1 & EMIF2 */ - while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ - || (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); + while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \ + || ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04)); /* Reprogram the DDR PYHY Control register */ /* PHY control values */ @@ -331,9 +333,9 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* No IDLE: BUG in SDC */ //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + //while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); + writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); /* * DMM : DMM_LISA_MAP_0(Section_0) @@ -347,8 +349,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, reset_phy(OMAP44XX_EMIF1_BASE); reset_phy(OMAP44XX_EMIF2_BASE); - *((volatile int *)0x80000000) = 0; - *((volatile int *)0x80000080) = 0; + writel(0, 0x80000000); + writel(0, 0x80000080); } void omap4_power_i2c_send(u32 r) |