Merge branch 'for-sha-mx35-3-stack-updates' of ssh://git.pengutronix.de/git/mkl/barebox into next

8 files changed, 304 insertions, 270 deletions

diff --git a/board/freescale-mx35-3-stack/3stack.c b/board/freescale-mx35-3-stack/3stack.c
index e54196617f..e6fa0f0472 100644
--- a/board/freescale-mx35-3-stack/3stack.c
+++ b/board/freescale-mx35-3-stack/3stack.c
@@ -60,8 +60,8 @@ static struct device_d cfi_dev = {
 };
 
 static struct fec_platform_data fec_info = {
-	.xcv_type = MII100,
-	.phy_addr = 0x1F,
+	.xcv_type	= MII100,
+	.phy_addr	= 0x1F,
 };
 
 static struct device_d fec_dev = {
@@ -71,8 +71,8 @@ static struct device_d fec_dev = {
 };
 
 static struct memory_platform_data sdram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
+	.name	= "ram0",
+	.flags	= DEVFS_RDWR,
 };
 
 static struct device_d sdram_dev = {
@@ -157,7 +157,7 @@ static int f3s_devices_init(void)
 	reg = readl(IMX_CCM_BASE + CCM_RCSR);
 	/* some fuses provide us vital information about connected hardware */
 	if (reg & 0x20000000)
-		nand_info.width = 2;	/* bit */
+		nand_info.width = 2;	/* 16 bit */
 	else
 		nand_info.width = 1;	/* 8 bit */
 
@@ -167,17 +167,17 @@ static int f3s_devices_init(void)
 	register_device(&nand_dev);
 	register_device(&cfi_dev);
 
-	switch ( (reg >> 25) & 0x3) {
+	switch ((reg >> 25) & 0x3) {
 	case 0x01:		/* NAND is the source */
 		devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
 		dev_add_bb_dev("self_raw", "self0");
-		devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+		devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
 		dev_add_bb_dev("env_raw", "env0");
 		break;
 
 	case 0x00:		/* NOR is the source */
 		devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
-		devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+		devfs_add_partition("nor0", 0x40000, 0x80000, PARTITION_FIXED, "env0");
 		protect_file("/dev/env0", 1);
 		break;
 	}
@@ -332,7 +332,7 @@ static int f3s_core_init(void)
 
 	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
 #define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x0);   /* for S0 */
+	writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
 	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
 	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
 	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
@@ -358,74 +358,84 @@ static int f3s_core_init(void)
 
 core_initcall(f3s_core_init);
 
-static int f3s_get_rev(struct i2c_client *client)
+static int f3s_get_rev(struct mc13892 *mc13892)
 {
-	u8 reg[3];
-	int rev;
+	u32 rev;
+	int err;
 
-	i2c_read_reg(client, 0x7, reg, sizeof(reg));
+	err = mc13892_reg_read(mc13892, MC13892_REG_IDENTIFICATION, &rev);
+	if (err)
+		return err;
 
-	rev = reg[0] << 16 | reg [1] << 8 | reg[2];
-	dev_info(&client->dev, "revision: 0x%x\n", rev);
+	dev_info(&mc13892->client->dev, "revision: 0x%x\n", rev);
+	if (rev == 0x00ffffff)
+		return -ENODEV;
 
-	/* just return '0' or '1' */
-	return !!((rev >> 6) & 0x7);
+	return ((rev >> 6) & 0x7) ? 20 : 10;
 }
 
-static void f3s_pmic_init_v2(struct i2c_client *client)
+static int f3s_pmic_init_v2(struct mc13892 *mc13892)
 {
-	u8 reg[3];
+	int err = 0;
 
-	i2c_read_reg(client, 0x1e, reg, sizeof(reg));
-	reg[2] |= 0x03;
-	i2c_write_reg(client, 0x1e, reg, sizeof(reg));
+	err |= mc13892_set_bits(mc13892, MC13892_REG_SETTING_0, 0x03, 0x03);
+	err |= mc13892_set_bits(mc13892, MC13892_REG_MODE_0, 0x01, 0x01);
+	if (err)
+		dev_err(&mc13892->client->dev,
+			"Init sequence failed, the system might not be working!\n");
 
-	i2c_read_reg(client, 0x20, reg, sizeof(reg));
-	reg[2] |= 0x01;
-	i2c_write_reg(client, 0x20, reg, sizeof(reg));
+	return err;
 }
 
-static void f3s_pmic_init_all(struct i2c_client *client)
+static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
 {
-	u8 reg[1];
+	int err = 0;
 
-	i2c_read_reg(client, 0x20, reg, sizeof(reg));
-	reg[0] |= 0x04;
-	i2c_write_reg(client, 0x20, reg, sizeof(reg));
+	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_INT_FLAG_1, 0x04, 0x04);
 
+	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_2, 0x80, 0x00);
 	mdelay(200);
+	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_2, 0x80, 0x80);
 
-	i2c_read_reg(client, 0x1a, reg, sizeof(reg));
-	reg[0] &= 0x7f;
-	i2c_write_reg(client, 0x1a, reg, sizeof(reg));
-
-	mdelay(200);
+	if (err)
+		dev_err(&mc9sdz60->client->dev,
+			"Init sequence failed, the system might not be working!\n");
 
-	reg[0] |= 0x80;
-	i2c_write_reg(client, 0x1a, reg, sizeof(reg));
+	return err;
 }
 
 static int f3s_pmic_init(void)
 {
-	struct i2c_client *client;
+	struct mc13892 *mc13892;
+	struct mc9sdz60 *mc9sdz60;
 	int rev;
 
-	client = mc13892_get_client();
-	if (!client)
-		return -ENODEV;
+	mc13892 = mc13892_get();
+	if (!mc13892) {
+		printf("FAILED to get mc13892 handle!\n");
+		return 0;
+	}
 
-	rev = f3s_get_rev(client);
-	if (rev) {
-		printf("i.MX35 CPU board version 2.0\n");
-		f3s_pmic_init_v2(client);
-	} else {
-		printf("i.MX35 CPU board version 1.0\n");
+	rev = f3s_get_rev(mc13892);
+	switch (rev) {
+	case 10:
+		break;
+	case 20:
+		f3s_pmic_init_v2(mc13892);
+		break;
+	default:
+		printf("FAILED to identify board revision!\n");
+		return 0;
 	}
+	printf("i.MX35 PDK CPU board version %d.%d\n", rev / 10, rev % 10);
 
-	client = mc9sdz60_get_client();
-	if (!client)
-		return -ENODEV;
-	f3s_pmic_init_all(client);
+	mc9sdz60 = mc9sdz60_get();
+	if (!mc9sdz60) {
+		printf("FAILED to get mc9sdz60 handle!\n");
+		return 0;
+	}
+
+	f3s_pmic_init_all(mc9sdz60);
 
 	return 0;
 }
@@ -442,4 +452,3 @@ void __bare_init nand_boot(void)
 	imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
 }
 #endif
-
diff --git a/board/freescale-mx35-3-stack/env/bin/_update b/board/freescale-mx35-3-stack/env/bin/_update
index fb7cbe8619..4f0839f89b 100644
--- a/board/freescale-mx35-3-stack/env/bin/_update
+++ b/board/freescale-mx35-3-stack/env/bin/_update
@@ -20,7 +20,7 @@ fi
 
 ping $eth0.serverip
 if [ $? -ne 0 ] ; then
-	echo "update aborted"
+	echo "Server did not reply! Update aborted."
 	exit 1
 fi
 
@@ -28,9 +28,12 @@ unprotect $part
 
 echo
 echo "erasing partition $part"
+echo
 erase $part
 
 echo
 echo "flashing $image to $part"
 echo
 tftp $image $part
+
+protect $part
diff --git a/board/freescale-mx35-3-stack/env/bin/boot b/board/freescale-mx35-3-stack/env/bin/boot
index dfb59aa692..fb2fe614d4 100644
--- a/board/freescale-mx35-3-stack/env/bin/boot
+++ b/board/freescale-mx35-3-stack/env/bin/boot
@@ -3,43 +3,53 @@
 . /env/config
 
 if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
+	rootfs_loc=nand
+	kernel_loc=nand
+elif [ x$1 = xnor ]; then
+	rootfs_loc=nor
+	kernel_loc=nor
+elif [ x$1 = xnet ]; then
+	rootfs_loc=net
+	kernel_loc=net
 fi
 
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$1 = xnor ]; then
-	root=nor
-	kernel=nor
-fi
 
 if [ x$ip = xdhcp ]; then
 	bootargs="$bootargs ip=dhcp"
-else
+elif [ x$ip != xno ]; then
 	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
 fi
 
-if [ x$root = xnand ]; then
-	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-elif [ x$root = xnor ]; then
-	bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+
+if [ $rootfs_loc != net ]; then
+	if [ x$rootfs_loc = xnand ]; then
+		rootfs_mtdblock=$rootfs_mtdblock_nand
+	else
+		rootfs_mtdblock=$rootfs_mtdblock_nor
+	fi
+
+
+	if [ $rootfs_type = ubifs ]; then
+		bootargs="$bootargs root=ubi0:root ubi.mtd=$rootfs_mtdblock"
+	else
+		bootargs="$bootargs root=/dev/mtdblock$rootfs_mtdblock"
+	fi
+
+	bootargs="$bootargs rootfstype=$rootfs_type"
 else
 	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
 fi
 
-bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;imx_nand:$nand_parts"
 
-if [ $kernel = net ]; then
+bootargs="$bootargs mtdparts=\"physmap-flash.0:$nor_parts;mxc_nand:$nand_parts\""
+
+if [ $kernel_loc = net ]; then
 	if [ x$ip = xdhcp ]; then
 		dhcp
 	fi
-	tftp $uimage uImage || exit 1
+	tftp $kernel uImage || exit 1
 	bootm uImage
-elif [ $kernel = nor ]; then
+elif [ $kernel_loc = nor ]; then
 	bootm /dev/nor0.kernel
 else
 	bootm /dev/nand0.kernel.bb
diff --git a/board/freescale-mx35-3-stack/env/bin/init b/board/freescale-mx35-3-stack/env/bin/init
index cdf0f6b8eb..c982f22a86 100644
--- a/board/freescale-mx35-3-stack/env/bin/init
+++ b/board/freescale-mx35-3-stack/env/bin/init
@@ -16,12 +16,13 @@ if [ -e /dev/nand0 ]; then
 	source /env/bin/hush_hack 
 fi
 
-#if [ -z $eth0.ethaddr ]; then
-#	while [ -z $eth0.ethaddr ]; do
-#		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-#	done
-#	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-#fi
+if [ -z $eth0.ethaddr ]; then
+	while [ -z $eth0.ethaddr ]; do
+		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+	done
+	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+	saveenv
+fi
 
 echo
 echo -n "Hit any key to stop autoboot: "
@@ -29,7 +30,7 @@ timeout -a $autoboot_timeout
 if [ $? != 0 ]; then
 	echo
 	echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
-	echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
+	echo "type update_rootfs nand|nor [<imagename>] to update rootfs into flash"
 	echo
 	exit
 fi
diff --git a/board/freescale-mx35-3-stack/env/bin/update_kernel b/board/freescale-mx35-3-stack/env/bin/update_kernel
index 05c822d860..63ad11aaed 100644
--- a/board/freescale-mx35-3-stack/env/bin/update_kernel
+++ b/board/freescale-mx35-3-stack/env/bin/update_kernel
@@ -1,8 +1,8 @@
 #!/bin/sh
 
 . /env/config
+image=$kernel
 
-image=$uimage
 if [ x$1 = xnand ]; then
 	part=/dev/nand0.kernel.bb
 elif [ x$1 = xnor ]; then
diff --git a/board/freescale-mx35-3-stack/env/bin/update_root b/board/freescale-mx35-3-stack/env/bin/update_rootfs
index eaf36ebcea..53dd2ca575 100644
--- a/board/freescale-mx35-3-stack/env/bin/update_root
+++ b/board/freescale-mx35-3-stack/env/bin/update_rootfs
@@ -2,7 +2,12 @@
 
 . /env/config
 
-image=$uimage
+if [ $rootfs_type = ubifs ]; then
+	image=${rootfs}.ubi
+else
+	image=${rootfs}.$rootfs_type
+fi
+
 if [ x$1 = xnand ]; then
 	part=/dev/nand0.root.bb
 elif [ x$1 = xnor ]; then
@@ -13,4 +18,3 @@ else
 fi
 
 . /env/bin/_update $2
-
diff --git a/board/freescale-mx35-3-stack/env/config b/board/freescale-mx35-3-stack/env/config
index 9fcb3dc7b9..51195f7404 100644
--- a/board/freescale-mx35-3-stack/env/config
+++ b/board/freescale-mx35-3-stack/env/config
@@ -1,28 +1,35 @@
 #!/bin/sh
 
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'no' if you don't want to pass the ip from barebox to the kernel
+#ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
 # can be either 'net', 'nor' or 'nand''
-kernel=net
-root=net
+kernel_loc=nand
+rootfs_loc=nand
 
-uimage=uImage-pcm038
-jffs2=root-pcm038.jffs2
+# can be either 'jffs2', or 'ubifs'
+rootfs_type=ubifs
+
+kernel=uImage-mx35-3-stack
+rootfs=root-mx35-3-stack
+envimage=u-boot-v2-environment-mx35-3-stack
 
 autoboot_timeout=3
 
-nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
+nfsroot="/path/to/nfs/root"
 bootargs="console=ttymxc0,115200"
 
-nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart_nor="/dev/mtdblock3"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart_nand="/dev/mtdblock7"
+bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW"
 
-# use 'dhcp' to do dhcp in barebox and in kernel
-ip=dhcp
+nor_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
+rootfs_mtdblock_nor=3
 
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
+nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
+rootfs_mtdblock_nand=7
diff --git a/board/freescale-mx35-3-stack/lowlevel_init.S b/board/freescale-mx35-3-stack/lowlevel_init.S
index 4e0a10293d..1680579b51 100644
--- a/board/freescale-mx35-3-stack/lowlevel_init.S
+++ b/board/freescale-mx35-3-stack/lowlevel_init.S
@@ -27,9 +27,9 @@
 #include <asm/cache-l2x0.h>
 #include "board-mx35_3stack.h"
 
-#define CSD0_BASE_ADDR             0x80000000
-#define ESDCTL_BASE_ADDR        0xB8001000
-#define CSD1_BASE_ADDR             0x90000000
+#define CSD0_BASE_ADDR		0x80000000
+#define ESDCTL_BASE_ADDR	0xB8001000
+#define CSD1_BASE_ADDR		0x90000000
 
 #define writel(val, reg) \
 	ldr		r0,	=reg;	\
@@ -42,84 +42,84 @@
 	strb		r1,	[r0];
 
 /* Assuming 24MHz input clock */
-#define MPCTL_PARAM_399     (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
-#define MPCTL_PARAM_532     ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
-#define PPCTL_PARAM_300     (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
+#define MPCTL_PARAM_399	(IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532	((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+#define PPCTL_PARAM_300	(IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
 
 	.section ".text_bare_init","ax"
 
-ARM_PPMRR:              .word   0x40000015
-L2CACHE_PARAM:          .word   0x00030024
-CCM_CCMR_W:             .word   0x003F4208
-CCM_PDR0_W:             .word   0x00001000
-MPCTL_PARAM_399_W:      .word   MPCTL_PARAM_399
-MPCTL_PARAM_532_W:      .word   MPCTL_PARAM_532
-PPCTL_PARAM_W:    	.word   PPCTL_PARAM_300
-CCM_BASE_ADDR_W:        .word   IMX_CCM_BASE
+ARM_PPMRR:		.word	0x40000015
+L2CACHE_PARAM:		.word	0x00030024
+CCM_CCMR_W:		.word	0x003F4208
+CCM_PDR0_W:		.word	0x00001000
+MPCTL_PARAM_399_W:	.word	MPCTL_PARAM_399
+MPCTL_PARAM_532_W:	.word	MPCTL_PARAM_532
+PPCTL_PARAM_W:		.word	PPCTL_PARAM_300
+CCM_BASE_ADDR_W:	.word	IMX_CCM_BASE
 
 .globl board_init_lowlevel
 board_init_lowlevel:
-	mov     r10, lr
+	mov	r10, lr
 
-	mrc 15, 0, r1, c1, c0, 0
+	mrc	15, 0, r1, c1, c0, 0
 
-	mrc 15, 0, r0, c1, c0, 1
-	orr r0, r0, #7
-	mcr 15, 0, r0, c1, c0, 1
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #7
+	mcr	15, 0, r0, c1, c0, 1
 
-	orr r1, r1, #(1<<11) /* Flow prediction (Z) */
-	orr r1, r1, #(1<<22) /* unaligned accesses  */
-	orr r1, r1, #(1<<21) /* Low Int Latency     */
+	orr	r1, r1, #(1 << 11)		/* Flow prediction (Z) */
+	orr	r1, r1, #(1 << 22)		/* unaligned accesses */
+	orr	r1, r1, #(1 << 21)		/* Low Int Latency */
 
-	mcr 15, 0, r1, c1, c0, 0
+	mcr	15, 0, r1, c1, c0, 0
 
-	mov r0, #0
-	mcr 15, 0, r0, c15, c2, 4
+	mov	r0, #0
+	mcr	15, 0, r0, c15, c2, 4
 
 	/*
-	 * Branch predicition is now enabled.  Flush the BTAC to ensure a valid
-	 * starting point.  Don't flush BTAC while it is disabled to avoid
+	 * Branch predicition is now enabled. Flush the BTAC to ensure a valid
+	 * starting point. Don't flush BTAC while it is disabled to avoid
 	 * ARM1136 erratum 408023.
 	 */
-	mov     r0, #0
-	mcr     p15, 0, r0, c7, c5, 6	/* flush entire BTAC */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 6		/* flush entire BTAC */
 
-	mov r0, #0
-	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
-	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
-	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+	mov	r0, #0
+	mcr	15, 0, r0, c7, c7, 0		/* invalidate I cache and D cache */
+	mcr	15, 0, r0, c8, c7, 0		/* invalidate TLBs */
+	mcr	15, 0, r0, c7, c10, 4		/* Drain the write buffer */
 
 	/* Also setup the Peripheral Port Remap register inside the core */
-	ldr r0, ARM_PPMRR        /* start from AIPS 2GB region */
-	mcr p15, 0, r0, c15, c2, 4
+	ldr	r0, ARM_PPMRR			/* start from AIPS 2GB region */
+	mcr	p15, 0, r0, c15, c2, 4
 
 /*
  * End of ARM1136 init
  */
-	ldr r0, CCM_BASE_ADDR_W
+	ldr	r0, CCM_BASE_ADDR_W
 
-	ldr r2, CCM_CCMR_W
-	str r2, [r0, #CCM_CCMR]
+	ldr	r2, CCM_CCMR_W
+	str	r2, [r0, #CCM_CCMR]
 
-	ldr r3, MPCTL_PARAM_532_W  /* consumer path*/
+	ldr	r3, MPCTL_PARAM_532_W		/* consumer path*/
 
-	/* Set MPLL , arm clock and ahb clock*/
-	str r3, [r0, #CCM_MPCTL]
+	/* Set MPLL, arm clock and ahb clock */
+	str	r3, [r0, #CCM_MPCTL]
 
-	ldr r1, PPCTL_PARAM_W
-	str r1, [r0, #CCM_PPCTL]
+	ldr	r1, PPCTL_PARAM_W
+	str	r1, [r0, #CCM_PPCTL]
 
-	ldr r1, CCM_PDR0_W
-	str r1, [r0, #CCM_PDR0]
+	ldr	r1, CCM_PDR0_W
+	str	r1, [r0, #CCM_PDR0]
 
-	ldr r1, [r0, #CCM_CGR0]
-	orr r1, r1, #0x00300000
-	str r1, [r0, #CCM_CGR0]
+	ldr	r1, [r0, #CCM_CGR0]
+	orr	r1, r1, #0x00300000
+	str	r1, [r0, #CCM_CGR0]
 
-	ldr r1, [r0, #CCM_CGR1]
-	orr r1, r1, #0x00000C00
-	orr r1, r1, #0x00000003
-	str r1, [r0, #CCM_CGR1]
+	ldr	r1, [r0, #CCM_CGR1]
+	orr	r1, r1, #0x00000C00
+	orr	r1, r1, #0x00000003
+	str	r1, [r0, #CCM_CGR1]
 
 	/* Skip SDRAM initialization if we run from RAM */
 	cmp	pc, #0x80000000
@@ -130,33 +130,33 @@ board_init_lowlevel:
 	mov	pc, r10
 
 1:
-	ldr r0, =ESDCTL_BASE_ADDR
-	mov r3, #0x2000
-	str r3, [r0, #0x0]
-	str r3, [r0, #0x8]
+	ldr	r0, =ESDCTL_BASE_ADDR
+	mov	r3, #0x2000
+	str	r3, [r0, #0x0]
+	str	r3, [r0, #0x8]
 
-	/* ip(r12) has used to save lr register in upper calling*/
-	mov fp, lr
+	/* ip(r12) has used to save lr register in upper calling */
+	mov	fp, lr
 
-	mov r5, #0x00
-	mov r2, #0x00
-	mov r1, #CSD0_BASE_ADDR
-	bl setup_sdram_bank
-	cmp r3, #0x0
-	orreq r5, r5, #1
-	eorne r2, r2, #0x1
-	blne setup_sdram_bank
+	mov	r5, #0x00
+	mov	r2, #0x00
+	mov	r1, #CSD0_BASE_ADDR
+	bl	setup_sdram_bank
+	cmp	r3, #0x0
+	orreq	r5, r5, #1
+	eorne	r2, r2, #0x1
+	blne	setup_sdram_bank
 
-	mov lr, fp
+	mov	lr, fp
 
-	ldr r3, =ESDCTL_DELAY_LINE5
-	str r3, [r0, #0x30]
+	ldr	r3, =ESDCTL_DELAY_LINE5
+	str	r3, [r0, #0x30]
 
 #ifdef CONFIG_NAND_IMX_BOOT
-	ldr	sp, =TEXT_BASE - 4	/* Setup a temporary stack in SDRAM */
+	ldr	sp, =TEXT_BASE - 4		/* Setup a temporary stack in SDRAM */
 
-	ldr	r0, =IMX_NFC_BASE		/* start of NFC SRAM                */
-	ldr	r2, =IMX_NFC_BASE + 0x800	/* end of NFC SRAM                  */
+	ldr	r0, =IMX_NFC_BASE		/* start of NFC SRAM */
+	ldr	r2, =IMX_NFC_BASE + 0x800	/* end of NFC SRAM */
 
 	/* skip NAND boot if not running from NFC space */
 	cmp	pc, r0
@@ -165,119 +165,119 @@ board_init_lowlevel:
 	bhs	ret
 
 	/* Move ourselves out of NFC SRAM */
-	ldr	r1, =TEXT_BASE
+	ldr r1, =TEXT_BASE
 
 copy_loop:
-	ldmia	r0!, {r3-r9}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r9}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
+	ldmia	r0!, {r3-r9}			/* copy from source address [r0] */
+	stmia	r1!, {r3-r9}			/* copy to   target address [r1] */
+	cmp	r0, r2				/* until source end addreee [r2] */
 	ble	copy_loop
 
-	ldr	pc, =1f			/* Jump to SDRAM                    */
+	ldr	pc, =1f				/* Jump to SDRAM */
 1:
-	bl	nand_boot		/* Load barebox from NAND Flash      */
+	bl	nand_boot			/* Load barebox from NAND Flash */
 
 	/* rebase the return address */
 	ldr	r1, =IMX_NFC_BASE - TEXT_BASE
-	sub	r10, r10, r1		/* adjust return address from NFC SRAM */
+	sub	r10, r10, r1			/* adjust return address from NFC SRAM */
 ret:
 #endif /* CONFIG_NAND_IMX_BOOT */
 
-	mov pc, r10
+	mov	pc, r10
 
 /*
  * r0: ESDCTL control base, r1: sdram slot base
- * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base
  */
 setup_sdram_bank:
-	mov r3, #0xE /*0xA + 0x4*/
-	tst r2, #0x1
-	orreq r3, r3, #0x300 /*DDR2*/
-	str r3, [r0, #0x10]
-	bic r3, r3, #0x00A
-	str r3, [r0, #0x10]
-	beq 2f
-
-	mov r3, #0x20000
-1:	subs r3, r3, #1
-	bne 1b
-
-2:	tst r2, #0x1
-	ldreq r3, =ESDCTL_DDR2_CONFIG
-	ldrne r3, =ESDCTL_MDDR_CONFIG
-	cmp r1, #CSD1_BASE_ADDR
-	strlo r3, [r0, #0x4]
-	strhs r3, [r0, #0xC]
-
-	ldr r3, =ESDCTL_0x92220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, =ESDCTL_PRECHARGE
-	strb r3, [r1, r4]
-
-	tst r2, #0x1
-	bne skip_set_mode
-
-	cmp r1, #CSD1_BASE_ADDR
-	ldr r3, =ESDCTL_0xB2220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, =ESDCTL_DDR2_EMR2
-	strb r3, [r1, r4]
-	ldr r4, =ESDCTL_DDR2_EMR3
-	strb r3, [r1, r4]
-	ldr r4, =ESDCTL_DDR2_EN_DLL
-	strb r3, [r1, r4]
-	ldr r4, =ESDCTL_DDR2_RESET_DLL
-	strb r3, [r1, r4]
-
-	ldr r3, =ESDCTL_0x92220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, =ESDCTL_PRECHARGE
-	strb r3, [r1, r4]
+	mov	r3, #0xE			/* 0xA + 0x4 */
+	tst	r2, #0x1
+	orreq	r3, r3, #0x300			/* DDR2 */
+	str	r3, [r0, #0x10]
+	bic	r3, r3, #0x00A
+	str	r3, [r0, #0x10]
+	beq	2f
+
+	mov	r3, #0x20000
+1:	subs	r3, r3, #1
+	bne	1b
+
+2:	tst	r2, #0x1
+	ldreq	r3, =ESDCTL_DDR2_CONFIG
+	ldrne	r3, =ESDCTL_MDDR_CONFIG
+	cmp	r1, #CSD1_BASE_ADDR
+	strlo	r3, [r0, #0x4]
+	strhs	r3, [r0, #0xC]
+
+	ldr	r3, =ESDCTL_0x92220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	ldr	r4, =ESDCTL_PRECHARGE
+	strb	r3, [r1, r4]
+
+	tst	r2, #0x1
+	bne	skip_set_mode
+
+	cmp	r1, #CSD1_BASE_ADDR
+	ldr	r3, =ESDCTL_0xB2220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	ldr	r4, =ESDCTL_DDR2_EMR2
+	strb	r3, [r1, r4]
+	ldr	r4, =ESDCTL_DDR2_EMR3
+	strb	r3, [r1, r4]
+	ldr	r4, =ESDCTL_DDR2_EN_DLL
+	strb	r3, [r1, r4]
+	ldr	r4, =ESDCTL_DDR2_RESET_DLL
+	strb	r3, [r1, r4]
+
+	ldr	r3, =ESDCTL_0x92220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	ldr	r4, =ESDCTL_PRECHARGE
+	strb	r3, [r1, r4]
 
 skip_set_mode:
-	cmp r1, #CSD1_BASE_ADDR
-	ldr r3, =ESDCTL_0xA2220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	strb r3, [r1]
-	strb r3, [r1]
-
-	ldr r3, =ESDCTL_0xB2220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	tst r2, #0x1
-	ldreq r4, =ESDCTL_DDR2_MR
-	ldrne r4, =ESDCTL_MDDR_MR
-	mov r3, #0xDA
-	strb r3, [r1, r4]
-	ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
-	streqb r3, [r1, r4]
-	ldreq r4, =ESDCTL_DDR2_EN_DLL
-	ldrne r4, =ESDCTL_MDDR_EMR
-	strb r3, [r1, r4]
-
-	cmp r1, #CSD1_BASE_ADDR
-	ldr r3, =ESDCTL_0x82228080
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-
-	tst r2, #0x1
-	moveq r4, #0x20000
-	movne r4, #0x200
-1:	subs r4, r4, #1
-	bne 1b
-
-	str r3, [r1, #0x100]
-	ldr r4, [r1, #0x100]
-	cmp r3, r4
-	movne r3, #1
-	moveq r3, #0
-
-	mov pc, lr
+	cmp	r1, #CSD1_BASE_ADDR
+	ldr	r3, =ESDCTL_0xA2220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	strb	r3, [r1]
+	strb	r3, [r1]
+
+	ldr	r3, =ESDCTL_0xB2220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	tst	r2, #0x1
+	ldreq	r4, =ESDCTL_DDR2_MR
+	ldrne	r4, =ESDCTL_MDDR_MR
+	mov	r3, #0xDA
+	strb	r3, [r1, r4]
+	ldreq	r4, =ESDCTL_DDR2_OCD_DEFAULT
+	streqb	r3, [r1, r4]
+	ldreq	r4, =ESDCTL_DDR2_EN_DLL
+	ldrne	r4, =ESDCTL_MDDR_EMR
+	strb	r3, [r1, r4]
+
+	cmp	r1, #CSD1_BASE_ADDR
+	ldr	r3, =ESDCTL_0x82228080
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+
+	tst	r2, #0x1
+	moveq	r4, #0x20000
+	movne	r4, #0x200
+1:	subs	r4, r4, #1
+	bne	1b
+
+	str	r3, [r1, #0x100]
+	ldr	r4, [r1, #0x100]
+	cmp	r3, r4
+	movne	r3, #1
+	moveq	r3, #0
+
+	mov	pc, lr