Remove all ARM __raw_* functions. They are mixed all over

the place. This clean up all ARM architectures to use only one set
of io functions.

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>

3 files changed, 32 insertions, 32 deletions

diff --git a/board/omap/board-beagle.c b/board/omap/board-beagle.c
index 0156cb70d7..e22f5c4eed 100644
--- a/board/omap/board-beagle.c
+++ b/board/omap/board-beagle.c
@@ -73,47 +73,47 @@ static void sdrc_init(void)
 {
        /* SDRAM software reset */
        /* No idle ack and RESET enable */
-       __raw_writel(0x1A, SDRC_REG(SYSCONFIG));
+       writel(0x1A, SDRC_REG(SYSCONFIG));
        sdelay(100);
        /* No idle ack and RESET disable */
-       __raw_writel(0x18, SDRC_REG(SYSCONFIG));
+       writel(0x18, SDRC_REG(SYSCONFIG));
 
        /* SDRC Sharing register */
        /* 32-bit SDRAM on data lane [31:0] - CS0 */
        /* pin tri-stated = 1 */
-       __raw_writel(0x00000100, SDRC_REG(SHARING));
+       writel(0x00000100, SDRC_REG(SHARING));
 
        /* ----- SDRC Registers Configuration --------- */
        /* SDRC_MCFG0 register */
-       __raw_writel(0x02584099, SDRC_REG(MCFG_0));
+       writel(0x02584099, SDRC_REG(MCFG_0));
 
        /* SDRC_RFR_CTRL0 register */
-       __raw_writel(0x54601, SDRC_REG(RFR_CTRL_0));
+       writel(0x54601, SDRC_REG(RFR_CTRL_0));
 
        /* SDRC_ACTIM_CTRLA0 register */
-       __raw_writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
+       writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
 
        /* SDRC_ACTIM_CTRLB0 register */
-       __raw_writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
+       writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
 
        /* Disble Power Down of CKE due to 1 CKE on combo part */
-       __raw_writel(0x00000081, SDRC_REG(POWER));
+       writel(0x00000081, SDRC_REG(POWER));
 
        /* SDRC_MANUAL command register */
        /* NOP command */
-       __raw_writel(0x00000000, SDRC_REG(MANUAL_0));
+       writel(0x00000000, SDRC_REG(MANUAL_0));
        /* Precharge command */
-       __raw_writel(0x00000001, SDRC_REG(MANUAL_0));
+       writel(0x00000001, SDRC_REG(MANUAL_0));
        /* Auto-refresh command */
-       __raw_writel(0x00000002, SDRC_REG(MANUAL_0));
+       writel(0x00000002, SDRC_REG(MANUAL_0));
        /* Auto-refresh command */
-       __raw_writel(0x00000002, SDRC_REG(MANUAL_0));
+       writel(0x00000002, SDRC_REG(MANUAL_0));
 
        /* SDRC MR0 register Burst length=4 */
-       __raw_writel(0x00000032, SDRC_REG(MR_0));
+       writel(0x00000032, SDRC_REG(MR_0));
 
        /* SDRC DLLA control register */
-       __raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
+       writel(0x0000000A, SDRC_REG(DLLA_CTRL));
 
        return;
 }
diff --git a/board/omap/board-sdp343x.c b/board/omap/board-sdp343x.c
index 130e6cec20..eb9d06c7ba 100644
--- a/board/omap/board-sdp343x.c
+++ b/board/omap/board-sdp343x.c
@@ -86,54 +86,54 @@ void board_init(void)
 static void sdrc_init(void)
 {
 	/* Issue SDRC Soft reset  */
-	__raw_writel(0x12, SDRC_REG(SYSCONFIG));
+	writel(0x12, SDRC_REG(SYSCONFIG));
     /* Wait until Reset complete */
-    while ((__raw_readl(SDRC_REG(STATUS)) & 0x1) == 0);
+    while ((readl(SDRC_REG(STATUS)) & 0x1) == 0);
     /* SDRC to normal mode */
-	__raw_writel(0x10, SDRC_REG(SYSCONFIG));
+	writel(0x10, SDRC_REG(SYSCONFIG));
 	/* SDRC Sharing register */
 	/* 32-bit SDRAM on data lane [31:0] - CS0 */
 	/* pin tri-stated = 1 */
-	__raw_writel(0x00000100, SDRC_REG(SHARING));
+	writel(0x00000100, SDRC_REG(SHARING));
 
 	/* ----- SDRC_REG(CS0 Configuration --------- */
 	/* SDRC_REG(MCFG0 register */
-	__raw_writel(0x02584019, SDRC_REG(MCFG_0));
+	writel(0x02584019, SDRC_REG(MCFG_0));
 
 	/* SDRC_REG(RFR_CTRL0 register */
-	__raw_writel(0x0003DE01, SDRC_REG(RFR_CTRL_0));
+	writel(0x0003DE01, SDRC_REG(RFR_CTRL_0));
 
 	/* SDRC_REG(ACTIM_CTRLA0 register */
-	__raw_writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0));
+	writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0));
 
 	/* SDRC_REG(ACTIM_CTRLB0 register */
-	__raw_writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0));
+	writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0));
 
 	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
-	__raw_writel(0x00000081, SDRC_REG(POWER));
+	writel(0x00000081, SDRC_REG(POWER));
 
 	/* SDRC_REG(Manual command register */
 	/* NOP command */
-	__raw_writel(0x00000000, SDRC_REG(MANUAL_0));
+	writel(0x00000000, SDRC_REG(MANUAL_0));
 	/* Precharge command */
-	__raw_writel(0x00000001, SDRC_REG(MANUAL_0));
+	writel(0x00000001, SDRC_REG(MANUAL_0));
 	/* Auto-refresh command */
-	__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
+	writel(0x00000002, SDRC_REG(MANUAL_0));
 	/* Auto-refresh command */
-	__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
+	writel(0x00000002, SDRC_REG(MANUAL_0));
 
 	/* SDRC MR0 register */
 	/* CAS latency = 3 */
 	/* Write Burst = Read Burst */
 	/* Serial Mode */
-	__raw_writel(0x00000032, SDRC_REG(MR_0));	/* Burst length =4 */
+	writel(0x00000032, SDRC_REG(MR_0));	/* Burst length =4 */
 
     /* SDRC DLLA control register */
 	/* Enable DLL A */
-	__raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
+	writel(0x0000000A, SDRC_REG(DLLA_CTRL));
 
     /* wait until DLL is locked  */
-    while ((__raw_readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
+    while ((readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
 	return;
 }
 
diff --git a/board/pcm037/pcm037.c b/board/pcm037/pcm037.c
index 2934a7712b..b1691e8fde 100644
--- a/board/pcm037/pcm037.c
+++ b/board/pcm037/pcm037.c
@@ -138,9 +138,9 @@ static void pcm037_usb_init(void)
 	u32 tmp;
 
 	/* enable clock */
-	tmp = __raw_readl(0x53f80000);
+	tmp = readl(0x53f80000);
 	tmp |= (1 << 9);
-	__raw_writel(tmp, 0x53f80000);
+	writel(tmp, 0x53f80000);
 
 	/* Host 1 */
 	tmp = readl(IMX_OTG_BASE + 0x600);